si4330 Silicon Laboratories, si4330 Datasheet - Page 5

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

Si4330
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I S T OF
IGURES
Figure 1. RX Application Example............................................................................................ 14
Figure 2. SPI Timing.................................................................................................................. 16
Figure 3. SPI Timing—READ Mode ..........................................................................................17
Figure 4. SPI Timing—Burst Write Mode .................................................................................. 17
Figure 5. SPI Timing—Burst Read Mode .................................................................................. 17
Figure 6. State Machine Diagram.............................................................................................. 18
Figure 7. RX Timing .................................................................................................................. 22
Figure 8. Frequency Deviation .................................................................................................. 26
Figure 9. Sensitivity at 1% PER vs. Carrier Frequency Offset .................................................. 27
Figure 10. PLL Synthesizer Block Diagram............................................................................... 31
Figure 11. FIFO Threshold ........................................................................................................33
Figure 12. Packet Structure....................................................................................................... 34
Figure 13. Required RX Packet Structure with Packet Handler Disabled ................................. 34
Figure 14. Multiple Packets in RX Packet Handler.................................................................... 35
Figure 15. Multiple Packets in RX with CRC or Header Error ................................................... 35
Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC .............................. 37
Figure 17. POR Glitch Parameters............................................................................................ 45
Figure 18. General Purpose ADC Architecture ......................................................................... 47
Figure 19. ADC Differential Input Example—Bridge Sensor ..................................................... 48
Figure 20. ADC Differential Input Offset for Sensor Offset Coarse Compensation................... 49
Figure 21. Temperature Ranges using ADC8 ........................................................................... 51
Figure 22. WUT Interrupt and WUT Operation.......................................................................... 54
Figure 23. Low Duty Cycle Mode .............................................................................................. 55
Figure 24. RSSI Value vs. Input Power..................................................................................... 58
Figure 25. Receiver—Schematic............................................................................................... 59
Figure 26. Receiver—Top .........................................................................................................61
Figure 27. Receiver—Top Silkscreen........................................................................................ 61
Figure 28. Receiver—Bottom .................................................................................................... 62
Figure 29. Sensitivity vs. Data Rate ..........................................................................................63
Figure 30. Receiver Selectivity.................................................................................................. 64
Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz ........................... 65
Figure 32. Synthesizer Phase Noise (VCOCURR = 11) ........................................................... 65
Figure 33. RX LNA Matching..................................................................................................... 67
Figure 34. QFN-20 Package Dimensions................................................................................ 140
Figure 35. QFN-20 Landing Pattern Dimensions .................................................................... 140
Preliminary Rev 0.2
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