si4330 Silicon Laboratories, si4330 Datasheet - Page 21

• Manufacturer Part Number: si4330
• Description: Si4330 Ism Receiver
• Manufacturer: Silicon Laboratories

3.3. Interrupts
The Si4330 is capable of generating an interrupt signal when certain events occur. The chip notifies the
microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt
signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits)
shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s)
(Registers 03h–04h) containing the active Interrupt Status bit; the nIRQ output signal will then be reset until the
next change in status is detected. All of the interrupts must be enabled by the corresponding enable bit in the
Interrupt Enable Registers (Registers 05h–06h). All enabled interrupt bits will be cleared when the microcontroller
reads the interrupt status register. If the interrupt is not enabled when the event occurs inside of the chip it will not
trigger the nIRQ pin, but the status may still be read correctly at anytime in the Interrupt Status registers.
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See “Register 03h. Interrupt/Status 1,” on page 72 and “Register 04h. Interrupt/Status 2,” on page 74 for a
complete list of interrupts.
3.4. Device Code
The device version code is readable from "Register 01h. Version Code (VC)". This is a read only register.
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03
04
05 R/W
06 R/W
01
R
R
R
Interrupt Enable 1
Interrupt Enable 2
Interrupt Status 1
Interrupt Status 2
Device Version
ion
enswdet enpreaval enpreainval
enfferr
iswdet
ifferr
D7
D7
0
Reserved Reserved
Reserved Reserved enrxffafull enext Reserved enpkvalid encrcerror
ipreaval
D6
D6
0
Preliminary Rev 0.2
ipreainval
D5
D5
0
vc[4]
D4
irxffafull
enrssi
irssi
D4
vc[3]
D3
enwut
iwut
iext Reserved ipkvalid
D3
vc[2]
D2
enlbd
ilbd
D2
vc[1]
D1
enchiprdy
ichiprdy
D1
vc[0]
D0
icrcerror
enpor
POR Def. Notes
ipor
Si4330
D0
00h
POR Def.
00h
01h
—
—
DV
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