st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 107

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

19.5 Parallel port timings
19.5.1 Dreq/Dack protocol
In this mode the two control pins PlinknotReq (Dreq) and PlinknotAck (Dack) are active low. The
initial (inactive) state of the two control wires is high.
Notes:
PLink is output t
PLink is input
PLink is input
or output
1
PlinknotReq
(Dreq)
PlinknotAck
(Dack)
PlinkData0-7
(Output)
PlinkData0-7
(Input)
This will be a maximum of 200 ns if the port is already programmed either to accept another
byte or to write another byte and the port has the data available. In the extreme case for a
PLink output this value could be very large if the link has to wait for other external accesses
to complete before it can read the data to write out through the PLink.
Figure 19.6 Byte-wide parallel port timings when using the Dreq/Dack protocol
Symbol Parameter
t
t
t
t
t
t
t
PALPDV
PAHDOX
PAHDOZ
PAHDIX
PALDIV
PAHPRL
PALPAH
PRLPAL
PlinknotAck falling transition to PlinkData valid
PlinkData hold time after rising edge of PlinknotAck
PlinkData output tristate time from PlinknotAck rising edge
PlinkData hold after PlinknotAck rising edge
PlinkData valid after PlinknotAck falling edge
PlinknotAck rising edge to succeeding PlinknotReq falling edge
PlinknotAck low time
Time between the input PlinknotReq falling and the output Plin-
knotAck falling
Table 19.5 Timings for Dreq/Dack protocol
t
PRLPAL
t
t
PALDIV
PALDOV
t
PALPAH
t
PAHDIX
t
t
PAHDOZ
PAHDOX
t
PAHPRL
Min
10
55
25
0
0
see
note 1
Max
100
340
90
20
ST20-GP1
107/116
Units
ns
ns
ns
ns
ns
ns
ns
ns