st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 28

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
5
The ST20-GP1 supports external interrupts, enabling an on-chip subsystem or external interrupt
pin to interrupt the currently running process in order to run an interrupt handling process.
The ST20-GP1 interrupt subsystem supports five prioritized interrupts. This allows nested pre-
emptive interrupts for real-time system design. Three interrupts are connected to on-chip
peripherals (2 for the UARTs, 1 for the programmable IO) and two are available as external
interrupt pins.
All interrupts are at a higher priority than the high priority process queue, see Figure 5.1. Each
interrupt level has a higher priority than the previous (interrupt 0 is lowest priority) and each level
supports only one software handler process.Note that interrupt handlers must not prevent the GPS
DSP data traffic from being handled. During continuous operation this has 1 ms latency and is not
a problem, but during initial acquisition it has a 32 s rate and thus all interrupts must be disabled
except if used to stop GPS operation.
Interrupts on the ST20-GP1 are implemented via an on-chip interrupt controller peripheral. An
interrupt can be signalled to the controller by one of the following:
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Interrupt controller
a signal on an external Interrupt pin
a signal from an internal peripheral or subsystem
software asserting an interrupt in a bit mask
Increasing
pre-emption
Interrupt 4
Interrupt1 pin
Interrupt 3
Interrupt0 pin
Interrupt 2
UART1
Interrupt 1
UART0
Interrupt 0
Programmable IO
High priority
process
Low priority
process
Figure 5.1 Interrupt priority