st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 59

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st20-gp1

Manufacturer Part Number
st20-gp1
Description
Gps Processor
Manufacturer
STMicroelectronics
Datasheet
status of the lock and stall bits. Table 9.6 shows the format of the EMIConfigStatus register.
EMIConfigStall register
The EMIConfigStall register can be used to stall the EMI. When set it prevents the EMI from
accepting further requests from the CPU or communications subsystems. Its main use is intended
to be in systems which anticipate turning the power off; the EMI must be inactive during such an
event, otherwise battery backed memory may be corrupted.
This register, once set, can only be cleared by resetting the ST20-GP1.
9.6
Table 9.8 shows the state of the EMI signals during reset. MemAddr2-19 are driven with a copy of
the value on the internal memory bus2-19.
Table 9.9 shows the configuration values for all banks during and after reset. If the BootSource0-1
pins indicate that the ST20-GP1 will boot from ROM, the BusWidth is set to the correct value as
the ST20-GP1 comes out of reset.
EMIConfigStatus
EMIConfigStall
Bit
0
31:6
Bit
0
1
2
3
4
5
Bit field
WrittenBank0
WrittenBank1
WrittenBank2
WrittenBank3
WriteLock
MemStall
Reset and bootstrap behavior
Bit field
EMIStall
EMI base address + #20
EMI base address + #30
Function
Bank 0 configuration has been written to using a devsw instruction.
Bank 1 configuration has been written to using a devsw instruction.
Bank 2 configuration has been written to using a devsw instruction.
Bank 3 configuration has been written to using a devsw instruction.
EMIConfigData0-3 registers are write protected.
EMIConfigStall has been set.
Reserved
Table 9.6 EMIConfigStatus register format
Table 9.7 EMIConfigStall register format
Table 9.8 EMI signal values during reset
Function
When set, this bit prevents the arbiter from granting any more accesses to the
memory subsystem.
Pins
MemAddr2-19
MemAddr1
notMemCE0-3
notMemOE0-1
notMemWB0-1
MemData0-15
Value
Valid
High
All high
All high
All high
High impedance
ST20-GP1
Write only
Read only
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