st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 92

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
15.4.3 Direct DMA protocol
In this mode the PLink becomes an unsynchronized (i.e. direct action) bus. The PlinknotAck
output still behaves as if it were acknowledging a real transfer. The PlinknotReq signal has no
effect in this mode of operation. In this mode PlinknotAck is active high. The initial (inactive) state
of the pin is low.
Direct mode output
To drive the output pins the PLink must be programmed to make a single byte DMA. If more than
one byte is output, the PLink will continue to drive the output pins as fast as the output DMA can
feed the data, i.e. once every 8 or more system clock cycles, until the correct number of bytes have
been output. The sequence of events for a single byte read is outlined below. When configured as
an output the drivers are always driven.
Note: At reset PlinknotAck is a logic one, appearing to the outside world as an ‘acknowledge’.
External logic will assume that the data has been read. Therefore after programming the PLink to
direct mode the PlinknotAck output falls.
Direct mode input
To read the input pins the PLink must be programmed to make a single byte DMA. The sequence
of events for a single byte read is outlined below.
92/116
1
2
1
PlinknotAck
PlinkData0-7
PlinknotAck
PlinkData0-7
The PLink forces the PlinknotAck pin high. The output pins are then driven with the new
data and the PlinknotAck pin is forced low.
The output data remains static and driven to the pads until either a new value is written as
output or until the link direction is changed. If the PLink returns to direct output mode, the
old data is once again driven to the pads.
The PLink forces the PlinknotAck pin high. The input pins are then read and the Plinkno-
tAck pin is forced low.
Figure 15.3 Direct DMA protocol
ST20 Output
ST20 Input
valid data