st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 64

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
LPAlarmLS and LPAlarmMS
The LPAlarmLS and LPAlarmMS registers are the least significant word and most significant word
of the LPAlarm register. This is used to program the low power alarm.
LPAlarmStart
A write to the LPAlarmStart register starts the low power alarm counter. The counter is stopped
and the LPStart register reset if either counter word (LPTimerLS and LPTimerMS) is written.
LPSysPll
The LPSysPll register controls the System Clock PLL operation when low power mode is entered.
This allows a compromise between wake-up time and power consumption during stand-by.
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LPAlarmLS
Bit
31:0
LPAlarmMS
Bit
7:0
LPAlarmStart
Bit
0
LPSysPll
Bit
1:0
Bit field
LPAlarmLS
Bit field
LPAlarmMS
Bit field
LPAlarmStart
Bit field
LPSysPll
LPC base address + #410
LPC base address + #414
LPC base address + #418
LPC base address + #420
Function
Least significant word of the low power alarm.
Function
Most significant word of the low power alarm.
Function
A write to this bit starts the low power alarm counter.
Function
Determines the system clock PLL when low power mode is entered, as follows:
Table 10.7 LPAlarmStart register format
Table 10.6 LPAlarmMS register format
Table 10.5 LPAlarmLS register format
LPSysPll1:0
Table 10.8 LPSysPll register format
00
01
10
11
System clock
PLL off
PLL reference on and power on
PLL reference on and power on
PLL on
Read/Write
Read/Write
Read/Write
Write