st20-gp1 STMicroelectronics, st20-gp1 Datasheet - Page 58

• Manufacturer Part Number: st20-gp1
• Description: Gps Processor
• Manufacturer: STMicroelectronics

ST20-GP1
9.5
Configuration parameters are stored in registers which are mapped into the device address space.
They may be accessed using devsw (device store word) and devlw (device load word) instructions.
The base addresses for the EMI registers are given in the Memory Map chapter.
EMIConfigData0-3 registers
The EMIConfigData0-3 registers contain configuration data for each of the EMI banks. The format
of each of the EMIConfigData0-3 registers is identical and is shown in Table 9.4.
EMIConfigLock register
The EMIConfigLock register is provided to write protect the EMIConfigData0-3 registers (further
writes to these registers are ignored). This bit is set by performing a devsw instruction to the given
address; the write data is ignored.
This register, once set, can only be cleared by resetting the ST20-GP1.
EMIConfigStatus register
The EMIConfigStatus register is provided to indicate which registers have been written to and the
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EMIConfigData0-3
Bit
0
3:1
4
8:5
10:9
14:11
18:15
22:19
26:23
30:27
31
EMIConfigLock
Bit
0
EMI configuration registers
Bit field
ConfigLock
Bit field
MemWaitEnable
DataDriveDelay
BusWidth
AccessDuration
BusReleaseTime
CEe1Time
CEe2Time
OEe1Time
WBe1Time
WBe2Time
Table 9.4 EMIConfigData0-3 register format - 1 per bank
EMI base address + #00, #04, #08, #0C
EMI base address + #10
Table 9.5 EMIConfigLock register format
Function
When set, the EMIConfigData0-3 registers are read only.
Function
Enables the MemWait pin.
Drive delay of data bus for writes.
Bus width of the bank (8 or 16 bits).
Duration of the external access.
Duration bus release time.
Delay from access start to notMemCE falling edge.
Delay from notMemCE rising edge to end of access.
Delay from access start to notMemOE falling edge.
Delay from access start to notMemWB falling edge.
Delay from notMemWB rising edge to end of access.
Reserved
BusWidth
0
1
Bank width
16 bits
8 bits
Read/Write
Write only
Units
Phases
Cycles
Cycles
Phases
Phases
Phases
Phases
Phases
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-
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