cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 10

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

3.0
4.0
The following subsections contain the following descriptions: command (CMD) and DQ bus (command and databus), database
entry, arbitration logic, pipeline and SRAM control, and full logic.
4.1
CMD[8:0] carries the command and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which is made up of data and mask fields that are organized as data and mask arrays. The DQ bus carries the Search data (of
the data and mask arrays and internal registers) during the Search command, as well as the address and data during Read or
Write operations. The DQ bus can also carry address information for the flow-through accesses to the external SRAMs or
SSRAMs.
4.2
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data mask bit. The on-chip priority encoder selects the first matching entry in the database that is nearest to
location 0.
4.3
When multiple search engines are cascaded to create large databases, the data being searched is presented simultaneously to
all search engines in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
Document #: 38-02042 Rev. *E
DQ[67:0]
Command Bus and DQ Bus
Database Entry (Data Array and Mask Array)
Arbitration Logic
Block Diagram
Functional Description
CMD[8:0]
CMDV
ACK
EOT
FULI[6:0]
PHS_L
CLK2X
RST_L
and PIO Access
ID[4:0]
Command
Decode
Full Logic
Search Successful Index Registers [7:0]
Global Mask Register Pairs [7:0]
Information and Command Register
Comparand Register Pairs [15:0]
[All registers are 68 bits wide.]
Next-free Address Register
FULL
Burst Read Register
Burst Write Register
CMD
Configurable as
Configurable as
FULO[1:0]
Compare/PIO Data
Mask Array
BHI[2:0]
Data Array
LHI[6:0]
16K x 68
8K x 136
4K x 272
16K x 68
8K x 136
4K x 272
Arbitration
Logic
Controller
LHO[1:0]
BHO[2:0]
SSF
SSV
TAP
Pipeline
Control
SRAM
and
CYNSE70032
TAP
SADR[21:0]
OE_L
WE_L
CE_L
ALE_L
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