cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 12

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

Table 5-1. CYNSE70032 Signal Description (continued)
Document #: 38-02042 Rev. *E
Cascade Interface
Device Identification
Supplies
Test Access Port
Parameter
FULO[1:0]
BHO[2:0]
FULI[6:0]
LHO[1:0]
TRST_L
BHI[2:0]
LHI[6:0]
ALE_L
ID[4:0]
OE_L
FULL
V
TDO
TMS
TCK
V
TDI
DDQ
DD
Type
n/a
n/a
O
O
O
O
T
T
T
I
I
I
I
I
I
I
I
[1]
SRAM Output Enable. This is the output-enable control for external SRAMs. Only the
last device drives this signal (with the LRAM bit set).
Address Latch Enable. When this signal is low, the addresses are valid on the SRAM
address bus. In a database of multiple CYNSE70032s, the ALE_L of all cascaded devices
must be connected. This signal is then driven by only one of the devices.
Local Hit In. These pins depth cascade the device to form a larger table. One signal of
this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block.
All unused LHI pins are connected to a logic 0. (For more information, see Section 14.0,
“Depth-Cascading” on page 96.)
Local Hit Out. LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the
LHO[0] is connected to one input of the LHI bus of up to four downstream devices in a
block of up to eight. (For more information see Section 14.0, “Depth-Cascading” on
page 96.)
Block Hit In. Inputs from the previous block BHO[2:0] are tied to the BHI[2:0] of the current
device. In a four-block system, the last block can contain only seven devices because the
identification code 11111 is used for broadcast access.
Block Hit Out. These outputs from the last device in a block are connected to the BHI[2:0]
inputs of the devices in the downstream blocks.
Full In. Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device
to generate the FULL flag for the depth-cascaded block.
Full Out. FULO[1] and FULO[0] are the same logical signal. One of these two signals
must be connected to the FULI of up to four downstream devices in a depth-cascaded
table. Bit[0] in the data array indicates whether the entry is full (1) or empty (0).This signal
is asserted if all bits in the data array are 1s. (Refer to Section 14.0, “Depth-Cascading”
on page 96, for information on how to generate the FULL flag.)
Full Flag. When asserted, this signal indicates that the table of multiple depth-cascaded
devices is full.
Device Identification. The binary-encoded device identification for a depth-cascaded
system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast
address that selects all cascaded search engines in the system. On a broadcast
Read-only, the device with the LDEV bit set to 1 responds.
Chip Core Supply. 1.8V.
Chip I/O Supply. 2.5V or 3.3V.
Test Access Port’s Test Data In.
Test Access Port’s Test Clock.
Test Access Port’s Test Data Out.
Test Access Port’s Test Mode Select.
Test Access Port’s Reset.
Description
CYNSE70032
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