cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 115

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

18.0
The CYNSE70032 supports the Test Access Port (TAP) and Boundary Scan Architecture, as specified in the IEEE JTAG standard
1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L.
Table 18-1 describes the operations that the test access port controller supports, and Table 18-2 describes the TAP Device ID
Register.
ground through a pull-down.
Table 18-1. Supported Operations
Document #: 38-02042 Rev. *E
SAMPLE/PRELOAD
Instruction
EXTEST
BYPASS
IDCODE
Note
CLAMP
JTAG (1149.1) Testing
HIghZ
. To disable JTAG functionality, connect the TCK, TMS and TDI pins to V
Figure 17-1. Sample Switch/Router Using the CYNSE70032 Device
Mandatory
Mandatory
Mandatory
Optional
Optional
Optional
Type
Sample/Preload. This operation loads the values of signals going to and from I/O
pins into the boundary scan shift register to provide a snapshot of the normal
functional operation, and to initialize the boundary scan.
External Test. This operation uses boundary scan values shifted in from TAP to
test connectivity external to the device.
This operation loads a single bit shift register between TDI and TDO and
provides a minimum-length serial path when no test operation is required.
This operation selects the Identification register between TDI and TDO and
allows the “idcode” to be read serially through TDO.
This operation drives preset values onto the outputs of devices.
This operation leaves the device output pins in a high impedance state.
Description
DDQ
through a pull-up, and TRST_L to
CYNSE70032
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