cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 106

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

15.6
SRAM Write enables write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed into the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1. Figure 15-8 shows the timing diagram. For the following description, the selected device refers to the only device in
the table as this is the only device that will be accessed.
At the end of cycle 3, a new command can begin. The write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
Document #: 38-02042 Rev. *E
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle.
because burst Writes into the SRAM are not supported.
address, with DQ[20:19] set to 10, to select the SRAM address.
Writes into the SRAM are not supported.
SRAM Write with a Table of One Device
SADR[21:0]
CMD[1:0]
CMD[8:2]
CLK2X
PHS_L
CMDV
ALE_L
WE_L
OE_L
CE_L
ACK
SSV
SSF
Figure 15-7. SRAM Readthrough Device Number 0 in a Bank of 31 Devices
DQ
0
1
1
1
z
0
0
Address
cycle
1
A B
Read
00
cycle
(Device Number 30 Timing)
2
cycle
3
cycle
4
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
Note
cycle
5
. CMD[2] must be set to 0 for SRAM Write, because burst
cycle
6
cycle
Note
7
z
z
z
z
. CMD[2] must be set to 0 for SRAM Write,
cycle
8
1
1
1
cycle
9
cycle
10
CYNSE70032
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