cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 26

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

Table 13-1. Search Latency from Instruction to SRAM Access Cycle
Search latency from command to SRAM access cycle is 4 for a single device in the table with TLSZ = 00. In addition, SSV and
SSF shift further to the right for different values of HLAT as specified in Table 13-2.
Table 13-2. Shift of SSF and SSV from SADR
13.2
The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-4. The following are the parameters
programmed into the eight devices.
Note
number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in
this case) must be programmed with LRAM = 0 and LDEV = 0.
Figure 13-5 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 0.
Figure 13-6 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 1.
Figure 13-7 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 7
(the last device in this specific table). For these timing diagrams four 68-bit searches are performed sequentially. HIT/MISS
assumptions were made as shown below in Table 13-3.
Table 13-3. HIT/MISS Assumption
Document #: 38-02042 Rev. *E
• First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
. All eight devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
Search Number
Number of Devices
1–31 (TLSZ = 10)
Devices 2–6
1–8 (TLSZ = 01)
68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70032 Devices
1 (TLSZ = 00)
Device 0
Device 1
Device 7
HLAT
000
001
010
100
101
011
110
111
Miss
Miss
Miss
Hit
1
Max Table Size
128K × 68 bits
496K × 68 bits
16K × 68 bits
Miss
Miss
Miss
Hit
2
Number of CLK Cycles
0
1
2
3
4
5
6
7
Miss
Hit
Hit
Hit
3
Latency in CLK Cycles
4
5
6
CYNSE70032
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Miss
Miss
Miss
Hit
4