cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 90

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

Note
The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR
Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is as shown in Figure 13-66. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of the
31 devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each
entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part
of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98).
to be location 0 in a four-entry page for 272-bit search (two LSBs of the matching index will be 00).
The Search command is a pipelined operation that executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle containing the C and D cycles is shown in Table 13-23.
Table 13-23. Search Latency from Instruction to SRAM Access Cycle
Search latency from command to SRAM access cycle is 6 only for a single device in the table with TLSZ = 10. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-24.
Table 13-24. Shift of SSF and SSV from SADR
Document #: 38-02042 Rev. *E
• Cycle D: The host ASIC continues to drive CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for a description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3
in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for ×272 tables.
. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
Number of Devices
1–31 (TLSZ = 10)
1–8 (TLSZ = 01)
1 (TLSZ = 00)
HLAT
Location
address
000
001
010
011
100
101
110
111
507900
GMR
12
L
0
4
8
K
271
271
A
0
(272-bit configuration)
Figure 13-66. x272 Table with 31 Devices
CFG = 10101010
B
1
Max Table Size
124K × 272 bits
32K × 272 bits
4K × 272 bits
C
2
D
3
Number of CLK Cycles
0
0
(First matching entry)
Must be same in each of the 31
0
1
2
3
4
5
6
7
Note
. The matching address is always going
devices
Latency in CLK Cycles
CYNSE70032
4
5
6
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