cynse70032 Cypress Semiconductor Corporation., cynse70032 Datasheet - Page 110

• Manufacturer Part Number: cynse70032
• Description: Network Search Engine
• Manufacturer: Cypress Semiconductor Corporation.

15.8
The following explains the SRAM Write operation done via a table(s) of up to 31 devices and with the following parameters:
TLSZ = 10. The diagram of this table(s) is shown in Figure 15-12. The following assumes that SRAM access is accomplished
through CYNSE70032 device number 0 (the selected device). Figure 15-13 and Figure 15-14 show the timing diagram for device
number 0 and device number 30, respectively.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
Document #: 38-02042 Rev. *E
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle.
because burst Writes into the SRAM are not supported.
address, with DQ[20:19] set to 10, to select the SRAM address.
Write
S
SRAM Write with Table(s) Consisting of up to 31 Devices
into the SRAM are not supported.
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
SADR[21:0]
CMD[1:0]
CMD[8:2]
Figure 15-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
ACK
SSV
SSF
DQ
0
1
z
0
0
1
1
Address
cycle
Write
1
A B
01
cycle
2
x
cycle
3
x
cycle
4
Note
cycle
5
. CMD[2] must be set to 0 for SRAM Write, because burst
cycle
6
1
Note
cycle
7
. CMD[2] must be set to 0 for SRAM Write,
z
z
z
z
cycle
8
1
0
1
1
cycle
9
cycle
10
CYNSE70032
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