nt1gt72u8pa1by Nanya Techology, nt1gt72u8pa1by Datasheet

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nt1gt72u8pa1by

Manufacturer Part Number
nt1gt72u8pa1by
Description
240pin Unbuffered Ddr2 Sdram Module With Ecc
Manufacturer
Nanya Techology
Datasheet
NT512T72U89A1BY / NT1GT72U8PA1BY
512MB: 64M x 72 / 1GB: 128M x 72
Unbuffered DDR2 SDRAM DIMM with ECC
240pin Unbuffered DDR2 SDRAM MODULE with ECC
Based on 64Mx8 DDR2 SDRAM
Features
• JEDEC Standard 240-pin Dual In-Line Memory Module
• 64Mx72 and 128Mx72 DDR2 Unbuffered DIMM based on
• Performance:
Intended for 333MHz applications
• Inputs and outputs are SSTL-18 compatible
• V
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• Bi-directional data strobe with one clock cycle preamble and
• Address and control signals are fully synchronous to positive
Description
NT512T72U89A1BY and NT1GT72U8PA1BY are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as a one-rank 64Mx72 and two ranks 128Mx72 high-speed memory array. Modules use nine
64Mx8 (NT512T72U89A1BY) and eighteen 64Mx8 (NT1GT72U8PA1BY) DDR2 SDRAMs in FBGA packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25”
long space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz clock speeds and achieves high-speed data transfer rates of up to
667MHz. Prior to any access operation, the device
DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
REV 1.3
08/2006
f
f
t
CK
CK
DQ
one-half clock post-amble
64Mx8 DDR2 SDRAM
NT512T72U89A1BY-3C
NT1GT72U8PA1BY-3C
DD
DIMM
= V
Clock Frequency
Clock Cycle
DQ Burst Frequency
Part Number
DDQ
Speed Sort
= 1.8Volt ± 0.1
Latency
*
PC2-5300
333MHz (3ns @ CL = 5)
-3C
333
667
5
3
MHz
MHz
Unit
ns
latency and burst type/ length/operation type must be programmed into the
Speed
DDR2-667
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
• Write Latency = Read Latency - 1
• Programmable Operation:
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 14/10/1 Addressing (row/column/bank) - NT512T72U89A1BY
• 14/10/2 Addressing (row/column/bank) - NT1GT72U8PA1BY
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• On Die Termination (ODT)
• Gold contacts
• SDRAMs in 84-ball FBGA Package
• RoHs Compliant product
clock edge
- Device
- Burst Type: Sequential or Interleave
- Burst Length: 4, 8
- Operation: Burst Read and Write
PC2-5300
Latency: 3, 4, 5
Organization
128Mx72
64Mx72
GOLD
Leads
© NANYA TECHNOLOGY CORP.
Power
1.8V
Note

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nt1gt72u8pa1by Summary of contents

Page 1

... Address and control signals are fully synchronous to positive Description NT512T72U89A1BY and NT1GT72U8PA1BY are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx72 and two ranks 128Mx72 high-speed memory array. Modules use nine 64Mx8 (NT512T72U89A1BY) and eighteen 64Mx8 (NT1GT72U8PA1BY) DDR2 SDRAMs in FBGA packages ...

Page 2

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Pin Description CK0, Differential Clock Inputs CKE0, CKE1 Clock Enable Row Address Strobe Column Address Strobe Write Enable , Chip Selects A0-A9, A11-A13 Address Inputs A10/AP Column Address Input/Auto-precharge ...

Page 3

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Pinout Pin Front Pin Front CB0 REF CB1 SS 3 DQ0 DQ1 DQS8 DQS0 48 CB2 CB3 SS 9 DQ2 ...

Page 4

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Input/Output Functional Description Symbol Type Polarity Positive CK0, CK1, CK2 (SSTL) Edge Negative , , (SSTL) Edge Active CKE0, CKE1 (SSTL) High Active , (SSTL) Low Active , , (SSTL) Low V Supply ...

Page 5

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR SDRAMs " $% " & $% & " $% & " & " $% & " $% & " & ...

Page 6

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Functional Block Diagram (1GB, 2 Ranks, 64Mx8 DDR SDRAMs " $% " & $% & " $% & " & " $% & " $% & " & ...

Page 7

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Serial Presence Detect (512MB) -- 64Mx72 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device ...

Page 8

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Serial Presence Detect (512MB) -- 64Mx72 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) ...

Page 9

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Serial Presence Detect (1GB) -- 128Mx72 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device ...

Page 10

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Serial Presence Detect (1GB) -- 128Mx72 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) ...

Page 11

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Absolute Maximum Ratings Symbol Voltage on I/O pins relative to Vss OUT Voltage on VDD supply relative to Vss V DD Voltage on VDDQ supply relative to Vss V DDQ Storage Humidity (without condensation) H STG Note: Stresses greater than those listed under “ ...

Page 12

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Operating, Standby, and Refresh Currents ° ° 1.8V ± 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) CASE DDQ DD Symbol Parameter/Condition Operating Current: one bank; active/precharge DQ, DM, and DQS inputs changing twice per clock cycle; address DD0 (MIN) ...

Page 13

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Operating, Standby, and Refresh Currents ° ° 1.8V ± 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) CASE DDQ DD Symbol Parameter/Condition Operating Current: one bank; active/precharge DQ, DM, and DQS inputs changing twice per clock cycle; address DD0 (MIN) ...

Page 14

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC AC Timing Specifications for DDR2 SDRAM Devices Used on Module ( ° ° 1.8V ± 0.1V; V CASE DDQ DD Symbol Parameter t DQ output access time from CK DQS output access time from CK/ ...

Page 15

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC AC Timing Specifications for DDR2 SDRAM Devices Used on Module ( ° ° 1.8V ± 0.1V; V CASE DDQ DD Symbol Parameter t Write recovery time without Auto-Precharge WR WR Write recovery time with Auto-Precharge ...

Page 16

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Package Dimensions (512MB, 1 Rank, 64Mx8 DDR SDRAMs ##+#" "+ " # +#" "+ ' +" &#+ + +" " +" " REV 1.3 08/2006 +!" " " ...

Page 17

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Package Dimensions (1GB, 2 Ranks, 64Mx8 DDR SDRAMs ##+#" "+ " # +#" "+ ' +" &#+ + +" " +" " REV 1.3 08/2006 +!" " " ...

Page 18

... NT512T72U89A1BY / NT1GT72U8PA1BY 512MB: 64M 1GB: 128M x 72 Unbuffered DDR2 SDRAM DIMM with ECC Revision Log Rev Date 0.1 07/2005 Preliminary Release 1.0 08/2005 Official Release 1.1 11/2005 Update SPD. 1.2 03/2006 Update Package Dimensions. 1.3 08/2006 Update Package Dimensions. REV 1.3 08/2006 Modification 18 NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. ...

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