NT2GC64B8HC0NS Nanya Techology, NT2GC64B8HC0NS Datasheet

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NT2GC64B8HC0NS

Manufacturer Part Number
NT2GC64B8HC0NS
Description
Un-buffered Ddr3 So-dimm
Manufacturer
Nanya Techology
Datasheet
PC3-8500 / PC3-10600
Un-buffered DDR3 SO-DIMM
NT2GC64B8HC0NS
Based on DDR3-1066/1333 128Mx8 (2GB) SDRAM C-Die
Features
•Performance:
DIMM CAS Latency
fck – Clock Freqency
tck – Clock Cycle
fDQ – DQ Burst Freqency
• 204-Pin Small Outline Dual In-Line Memory Module (SO-DIMM)
• 2GB: 256Mx64 Unbuffered DDR3 SO-DIMM based on 128Mx8
• Intended for 533MHz/667MHz applications
• Inputs and outputs are SSTL-15 compatible
• V
• SDRAMs have 8 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock transitions.
• Address and control signals are fully synchronous to positive
Description
NT2GC64B8HC0NS is un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Small Outline Dual In-Line Memory Module
(SO-DIMM), organized as two ranks of 256Mx64 (2GB) high-speed memory array. Modules use sixteen 128Mx8 (2GB) 78-ball BGA
packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of
these common design files minimizes electrical variation between suppliers. All NANYA DDR3 SODIMMs provide a high-performance,
flexible 8-byte interface in a space-saving footprint.
The DIMM is intended for use in applications operating of 533MHz/667MHz clock speeds and achieves high-speed data transfer rates of
1066Mbps/1333Mbps. Prior to any access operation, the device  latency and burst/length/operation type must be programmed into the
DIMM by address inputs A0-A13 (2GB) and I/O inputs BA0~BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data
are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.0
12/2009
DDR3 SDRAM A-Die devices.
clock edge
DD
= V
Speed Sort
DDQ
= 1.5V ±0.075V
PC3-8500
1.875
1066
-BE
533
7
PC3-10600
1333
-CG
667
1.5
9
Mbps
MHz
Unit
ns
1
• Programmable Operation:
• Two different termination values (Rtt_Nom & Rtt_WR)
• 14/10/2 (row/column/rank) Addressing for 2GB
• Extended operating temperature rage
• Auto Self-Refresh option
• Serial Presence Detect
• Gold contacts
• 2GB: SDRAMs are in 78-ball BGA Package
• RoHS compliance + Halogen Free
- DIMM  Latency: 6,7,8,9
- Burst Type: Sequential or Interleave
- Burst Length: BC4, BL8
- Operation: Burst Read and Write
NANYA reserves the right to change products and specifications without notice.
© NANYA TECHNOLOGY CORPORATION

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NT2GC64B8HC0NS Summary of contents

Page 1

... Description NT2GC64B8HC0NS is un-buffered 204-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Small Outline Dual In-Line Memory Module (SO-DIMM), organized as two ranks of 256Mx64 (2GB) high-speed memory array. Modules use sixteen 128Mx8 (2GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers ...

Page 2

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Ordering Information Part Number NT2GC64B8HC0NS-BE DDR3-1066 PC3-8500 NT2GC64B8HC0NS-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line ,  Clock Inputs, negative line CKE0, CKE1 Clock Enable  ...

Page 3

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS DDR3 SDRAM Pin Assignment Pin Front Pin Back Pin REFDQ DQ4 DQ0 6 DQ5 57 7 DQ1  DM0 12 DQS0 ...

Page 4

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Input/Output Functional Description Symbol Type Polarity CK0, CK1 Cross Input ,  point Active CKE0, CKE1 Input High Active ,  Input Low Active   ...

Page 5

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Functional Block Diagram – [2GB 2 Ranks, 128Mx8 DDR3 SDRAMs] 240ohm +/-1% DQS3 DQS ZQ   DM3 DM DQ[24:31] DQ[0:7] D11 240ohm +/-1% DQS1 DQS ZQ   DM1 DM DQ[8:15] DQ[0:7] D1 240ohm +/-1% DQS0 ...

Page 6

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Serial Presence Detect (Part [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs] Byte Description 0 CRC range, EEPROM bytes, bytes used 1 SPD revision 2 DRAM device type 3 Module type (form factor) 4 SDRAM Device density and banks 5 SDRAM device row and column count ...

Page 7

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Serial Presence Detect (Part [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs] Byte Description 128-145 Module part number 146 Module die revision 147 Module PCB revision DRAM device manufacturer 148-149 ID 150-175 Manufacturer reserved 176-255 Customer reserved REV 1 ...

Page 8

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Environmental Requirements Symbol Operating Temperature (ambient) T OPR Storage Temperature T STG Note: Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability ...

Page 9

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Single-Ended AC and DC Input Levels for Command and Address Symbol Parameter VIH.CA(DC) DC Input Logic High VIL.CA(DC) DC Input Logic Low VIH.CA(AC) AC Input Logic High VIL.CA(AC) AC Input Logic Low VIH.CA(AC150) AC Input Logic High VIL.CA(AC150) AC Input Logic Low ...

Page 10

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Operating, Standby, and Refresh Currents = 1.5V ± 0.075V [2GB – 2 Ranks, 128Mx8 DDR3 SDRAMs ° ° CASE DDQ DD Symbol Operating One Bank Active-Precharge Current IDD0 Operating One Bank Active-Read-Precharge Current IDD1 Precharge Power-Down Current Slow Exit ...

Page 11

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Standard Speed Bins Speed Bin CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay PRE command period ACT to ACT or REF command period ACT to PRE command period CL CWL 7 7,8 8 ...

Page 12

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS AC Timing Specifications for DDR3 SDRAM Devices Used on Module Symbol Parameter Clock Timing tCK(DLL_OF Minimum Clock Cycle Time (DLL off mode) tCK(avg) Average Clock Period(Refer to "Standard Speed tCH(avg) Average high pulse width tCL(avg) Average low pulse width ...

Page 13

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Symbol Parameter Command and Address Timing tDLLK DLL Locking time Internal READ command to PRECHARGE tRTP Command delay Delay from start of internal write transaction to tWTR internal read command tWR WRITE recovery time tMRD Mode Register Set command cycle time ...

Page 14

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Symbol Parameter Timing of WR command to Power Down entry tWRPDEN (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry tWRAPDEN (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry tWRPDEN (BC4MRS) Timing of WRA command to Power Down entry ...

Page 15

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Package Dimensions – [NT2GC64B8HC0NS, 2GB 2 Ranks, 128Mx8 DDR3 SDRAMs] 2.0 (0.079) 1 21.0 (0.827) 1.5 (0.059) Detail A Units: Millimeters (Inches) Note: Device position and scale are only for reference. Revision Log REV 1.0 12/2009 67.60 +/- 0.15 (2.661 +/- 0.006) 63.60 (2.504) 203 Detail A Detail B 39 ...

Page 16

... PC3-8500 / PC3-10600 Un-buffered DDR3 SO-DIMM NT2GC64B8HC0NS Rev Date 0.1 10/2009 Preliminary Release 1.0 12/2009 Official Release Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: Printed in Taiwan © 2009 REV 1 ...

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