nt1gt72u4pb0bv Nanya Techology, nt1gt72u4pb0bv Datasheet

nt1gt72u4pb0bv

Manufacturer Part Number

nt1gt72u4pb0bv

Description

240pin Registered Ddr2 Sdram Module Based On 64mx8 & 128mx4 Ddr2 Sdram Die B

Manufacturer

Nanya Techology

Datasheet

1.NT1GT72U4PB0BV.pdf (25 pages)

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NT2GT72U4NB0BV / NT2GT72U4NB1BV

NT512T72U89B0BV / NT1GT72U4PB0BV

512MB: 64M x 72 / 1GB: 128M X 72 / 2GB: 256M X 72

Registered DDR2 SDRAM DIMM

240pin Registered DDR2 SDRAM MODULE

Features

REV 1.3

05/2007

• 64Mx72 Registered DDR2 DIMM based on 64Mx8 DDR2

• 128Mx72 & 256Mx72 Registered DDR2 DIMM based on

• JEDEC Standard 240-pin Dual In-Line Memory Module

• Error Check Correction (ECC) Support

• Registered inputs with one-clock delay

• Performance:

• Intended for 333 and 400 MHz applications

• Inputs and outputs are SSTL-18 compatible

• V

• SDRAMs have 4 internal banks for concurrent operation

Description

NT512T72U89B0BV, NT1GT72U4PB0BV, NT2GT72U4NB0BV and NT2GT72U4NB1BV are Registered 240-Pin Double Data Rate 2

(DDR2) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 64Mx72 or128Mx72 and two-banks

256Mx72 high-speed memory array. The module uses nine 64Mx8 (NT512T72U89B0BV), eighteen 128Mx4 (NT1GT72U4PB0BV) or

thirty-six 128Mx4 (NT2GT72U4NB0BV, NT2GT72U4NB1BV) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using

raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation

between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving

footprint.

The DIMM is intended for use in applications operating up to 333 MHz (400MHz) clock speeds and achieves high-speed data transfer

rates of up to 667 MHz (800MHz). Prior to any access operation, the device

programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of

serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.

SDRAM (NT5TU64M8BE)

128Mx4 DDR2 SDRAM (NT5TU128M4BE)

DIMM

= 1.8 ± 0.1 Volt, V

Clock Frequency

Clock Cycle

DQ Burst Frequency

Speed Sort

Latency

DDQ

= 1.8 ± 0.1 Volt

PC2-5300 PC2-6400 PC2-6400

333

667

-3C

-25D

400

800

2.5

-25C

400

800

2.5

MHz

Unit

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Based on 64Mx8 & 128Mx4 DDR2 SDRAM Die B

• Differential clock inputs

• Data is read or written on both clock edges

• Programmable Operation:

• Auto Refresh (CBR) and Self Refresh Modes

• On-Die Termination (ODT)

• Off-Chip Driver (OCD)

• 14/10/1 Addressing (row/column/rank) – 512MB

• 14/11/1 Addressing (row/column/rank) – 1GB

• 14/11/2 Addressing (row/column/rank) – 2GB

• Serial Presence Detect

• Gold contacts

• SDRAMs in 60-ball FBGA Package

• RoHS compliance

- Device

- Burst Type: Sequential or Interleave

- Burst Length: 4, 8

- Operation: Burst Read and Write

latency and burst/length/operation type must be

Latency: 5, 6

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