nt1gc64b88a0nf Nanya Techology, nt1gc64b88a0nf Datasheet - Page 4

• Manufacturer Part Number: nt1gc64b88a0nf
• Description: Based On Ddr3-1066/1333 128mx8 Sdram A-die
• Manufacturer: Nanya Techology

NT1GC64B88A0NF / NT2GC64B8HA0NF
1GB: 128M x 64 / 2GB: 256M x 64
PC3-8500 / PC3-10600
Unbuffered DDR3 SDRAM DIMM
Input/Output Functional Description
REV 1.2
06/2009
BA0, BA1, BA2
V

DQS0 – DQS8
 – 
V
ODT0, ODT1
CKE0, CKE1
DQ0 – DQ63
DD
DM0 – DM8
SA0 – SA2
REFDQ,
CK0, CK1
, 
Symbol
A0 – A9
,
A10/AP
A12/


, 
,
V
SDA
SCL
A11
A13

DDSPD,
V
REFCA
,

V
SS
Supply
Supply
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
Polarity
Active
Active
Active
Active
Active
Cross
Cross
point
point
High
High
High
Low
Low
-
-
-
-
-
-
-
-
-
-
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enables the associated DDR3 SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored but
previous operations continue, Rank 0 is selected by ; Rank 1 is selected by 
When sampled at the positive rising edge of CK and falling edge of , signals 
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to V
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The  pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM
SS
and DDR3 SDRAM mode registers programmed appropriately.
4
NANYA reserves the right to change products and specifications without notice.
Function
DDSPD
on the system planar to act as a pull
© NANYA TECHNOLOGY CORPORATION
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
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