pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 157

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Figure 58 shows a diagram of the interrupt sources and associated enable bits.
The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETI), Enable Receive Interrupt (ERI)
and Enable Receive Error Interrupt (EEI) bits in UICTRL register.
A transmit interrupt is generated when both the TBE and ETI bits are set. To remove this interrupt, the software must either
disable the interrupt by clearing the ETI bit or write to UTBUF register (thus clearing the TBE bit).
A receive interrupt is generated on two conditions:
DMA Support
The USART can operate with either one or two DMA channels. Two DMA channels are required for processor-independent
full-duplex operation. Both receive and transmit DMA can be enabled individually.
If the transmit DMA is enabled (ETD=1), the USART issues a DMA request every time the TBE flag is set. Enabling the
transmit DMA automatically disables the TX interrupt independent of the value of the ETI bit.
Enabling the receive DMA (ERD=1) causes a DMA request to be asserted every time the Receive Buffer Full flag (RBF) is
set. Once the receive DMA is enabled the RX interrupt is automatically disabled independent of the value of the ERI bit.
However, to detect errors during reception the receive error interrupt should be enabled (EEI=1) while using the DMA.
Break Generation and Detection
A line break is generated when BRK bit is set in MDSL register. The UTXD line remains low until the user resets the BRK bit.
A line break is detected if URXD remains low for a time equivalent to 10 bit times or longer, after a missing stop bit has been
detected.
Parity Generation and Detection
Parity is only generated or checked with 7- and 8-bit data formats. It is not generated or checked in Diagnostic Loopback
mode, Attention mode or in Normal mode with 9-bit data format. Parity generation and checking is enabled and disabled via
PEN bit in UFRS register. PSEL bits in UFRS register are used to select odd, even, mark or space parity.
ISE Mode Operation
The USART module supports breakpoint operation by preserving some of the status bits of the USTAT and UICTRL regis-
ters. While the FREEZE bit is asserted, the PE, FE, DOE, BKD and DCTS bits are not cleared on a read of STAT register.
If both the RBF and ERI bits are set. To remove this interrupt, the software must either disable the interrupt, by clear-
ing the ERI bit, or read from URBUF register (thus clearing the RBF bit).
If both the ERR and the EEI bits are set. To remove this interrupt, the software must either disable it by clearing the
EEI bit, or read USTAT register, which causes ERR flag to be cleared.
DOE
FE
PE
Figure 58. USART Interrupt Sources
(Continued)
ERR
TBE
RBF
157
EEI
ERI
ETI
RX
Interrupt
TX
Interrupt
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