pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 175

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
In this state, all ADC activities are halted and ADC current consumption from the AV
ADC causes an activation delay.
It is recommended to disable the ADC only after the buffer registers of all four channels have been read.
Interrupt Structure
The ADC Interrupt is a level high interrupt, generated if one (or more) of the events in Table 23 becomes active. The ADC
interrupt is connected to the ICU.
When an event flag and its related mask bit are set (enabled), the ADC Interrupt request is asserted. This is indicated by
a high level of the ADC Interrupt signal.
The software must reset the event flag (or reset its mask bit) in order to deassert the ADC Interrupt request.
All the interrupt mask bits (interrupt disabled), the data-related event flags (EOCEV and the four DATVAL bits) and the con-
nection-failure event flag (OPSHEV) are cleared by both reset conditions. The overtemperature event flag (OTSEV) is
cleared only by V
The ADC Interrupt is routed to the ICU as an ADCI signal (see Section 4.3 on page 98).
ADC Operating Principles
Measurement Sequence. The following measurements are executed, in the order listed, during one ADC cycle for all en-
abled channels:
1. Temperature measurement, from the input indicated by SELIN field in TCHANCTL register. The A/D conversion starts
2. Voltage measurement for Voltage Channel 1, from the input selected by SELIN field in VCHN1CTL register. The A/D
3. Voltage measurement for Voltage Channel 2, as above, using the VCHN2CTL and VCHN2DAT registers.
4. Voltage measurement for Voltage Channel 3, as above, using the VCHN3CTL and VCHN3DAT registers.
5. End of the ADC cycle. EOCEV bit in ADCSTS register is set (in addition to all the relevant DATVAL bits).
The software may read the measurement result for each channel immediately after its DATVAL bit is set. Alternatively, the
results may be read at the end of the cycle when EOCEV bit is set. After the data in VCHNiDAT register is read, the software
should clear the relevant DATVAL bit to indicate that the data in the buffers has been read.
The ADC cycle duration may be calculated using the formula below (N is the number of enabled voltage channels):
Where:
by selecting the input and waiting for the time period (TMPDLY delay) set in ADLYCTL register. The resulting 8-bit digital
value is stored in TCHANDAT register, and DATVAL bit in TCHANCTL register is set.
conversion starts by selecting the input and waiting for the time period (VOLDLY delay) set in ADLYCTL register. The
resulting 10-bit digital value is stored in VCHN1DAT register, and DATVAL bit in VCHN1CTL register is set. Note: This
measurement is skipped if Voltage Channel 1 is disabled by setting the SELIN field in VCHN1CTL register to 1F
T
Event Flag
t
t
t
t
OPSHEV
TD
TC
VD
VC
ADC cycle
DATVAL
DATVAL
DATVAL
DATVAL
EOCEV
OTSEV
- Temperature Conversion Delay Time
- Temperature Conversion Time
- Voltage Conversion Delay Time
- Voltage Conversion time
CC
= 2
Power-Up Reset.
TCHANCTL
VCHN1CTL
VCHN2CTL
VCHN3CTL
Mnemonic
Register
ADCSTS
ADCSTS
ADCSTS
*
(t
TD
+ t
INTOSEN
INTOTEN
INTECEN
INTDVEN
INTDVEN
INTDVEN
INTDVEN
Mask Bit
TC
) + (N+1)
Table 23. ADC Interrupt Structure
(Continued)
TCHANCTL Data Valid Event/Enable (Temperature Channel)
VCHN1CTL Data Valid Event/Enable (Voltage Channel 1)
VCHN2CTL Data Valid Event/Enable (Voltage Channel 2)
VCHN3CTL Data Valid Event/Enable (Voltage Channel 3)
Mnemonic
ADCCNF
ADCCNF
ADCCNF
Register
*
(t
175
VD
Open/Short Event/Enable
Overtemperature Event/Enable
End-of-Cycle Event/Enable
+ t
VC
)
CC
Description
is reduced. Note that re-enabling the
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