pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 70

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
On write cycles of a single byte, the remaining eight bits of the bus are floating.
On read cycles of a single byte, the remaining eight bits of the bus are ignored. There is no need for external pull-up resistors.
Clock and Bus Cycles
There are two types of bus cycles: data transfer and non-data transfer. Data transfer bus cycles cause transfer of data from
or to the memory device. Non-data transfer bus cycles (described in Section 4.1.9 on page 81) are used for observability of
internal bus transactions and do not involve data transfer from or to external devices.
There are four types of data transfer bus cycles:
The BIU uses EWR configuration bit in BCFG register to select the early or late write data transfer bus cycle. It uses FRE in
SZCFGn register (where “n” refers to zone 0, 1 or 2) to select normal read or fast read data transfer bus cycles.
The basic late write bus cycle takes two clock cycles. The basic early write bus cycle takes three clock cycles. When the BIU
uses the early write bus cycle, the RD signal is not required for interfacing with the memory device (with the exception of
flash). On reset, the early write bus cycle is configured.
The basic normal read bus cycle takes two clock cycles. Fast read bus cycle always takes one clock cycle. On reset, the
normal read bus cycle is configured.
Notes:
1. In the descriptions that follow, the “n” in SELn signal refers to two of the three available BIU select signals (numbered 0
2. For all timing diagrams, the value of BST0-2 depends on the type of core bus transaction.
3. In the following paragraphs, SZCFGn refers to three of the four BIU zone configuration registers (n = 0, 1 or 2) - the fourth
Early write
Late write
Normal read
Fast read
or 1, corresponding to zone 0 or zone 1 respectively). The third signal is labelled SELIO.
configuration register is labelled IOCFG.
Number of
Number of
1. Burst bus cycle, if burstable; otherwise, the core transaction is
Bytes
Bytes
broken into “basic” bus cycles.
1
1
2
2
1
1
2
2
Table 14. Bus Cycles of an 8-Bit Data Bus
Table 13. Bus Cycles of a 16-Bit Data Bus
Transferred Core
Transferred Core
B1
B1
B1
B1
B1
B1
Bus Bytes
Bus Bytes
(Continued)
B0
B0
B0
B0
B0
B0
70
Address (LSB)
Address (LSB)
Then 1
Then 0
Then 0
0
1
0
1
0
1
0
1
Data Bus Pins
Data Bus Pins
8-15
0-15
8-15
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
1
Revision 1.07