pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 77

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
4.0 Embedded Controller Modules
When no T
same zone follows. The RD signal is always deactivated in the clock cycle following T2; see Figures 18, 19 and 20.
A burst bus cycle supplements the basic read bus cycle if the core attempts to access more bytes (i.e., a word) than the
configured bus width (and BRE in SZCFGn register is set to 1). The burst bus cycle (T2B) follows T2 before the T
(if configured). A wait clock cycle (TBW) is added between T2 and T2B if WBR in SZCFGn register is set to 1.
The address of the burst bus cycle is changed on TBW (if configured) or T2B (if no TBW). At the end of T2B, data is sampled.
The RD signal is activated during the burst bus cycle and is deactivated in the clock cycle following T2B; see Figures 21 and
22.
Figure 18. Two Basic Normal Read Bus Cycles with Idle In Between (IPST Bit in SZCFGy Register = 1,
hold
cycles are specified, SELn is deactivated in the clock cycle that follows T2, unless another read from the
Bus State
Bus State
BST0-2
CLK
A0-19
SELn
D0-15
RD
WR0-1
CLK
A0-19
SELx
SELy
D0-15
RD
WR0-1
BST0-2
(x
(y
Figure 19. Normal Read Bus Cycle with 2 Internal Waits and 1 Hold
y)
x)
Normal Read
T1
IPRE Bit in SZCFGx Register = 1)
T2
T1
(Continued)
In
T
TIW
Idle
77
TIW
T1
Normal Read
T2
T2
In
In
T
Hold
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hold
cycles