pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 343

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
6.0 Host-Controlled Modules and Host Interface
1. START: 1110
2. ID field: FWH ID nibble (compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on
3. Address: Eight address nibbles MS nibble first (see usage below).
4. DATA: Two data nibbles, LS nibble first (D3-D0, D7-D4).
5. TAR (two cycles).
6. SYNC.
7. TAR (two cycles).
The ID field is compared with bits 7-4 of shared memory; see “Shared Memory Configuration Register” on page 351. If the
two match, the PC87591x continues handling the transaction; if they do not match, the current LPC-FWH transaction is ig-
nored.
LPC-FWH Address translation: The address field in the LPC-FWH transaction is constructed of eight nibbles. The first seven
correspond to the first LS seven address nibbles (A27-A0) as follows: The first nibble that appears corresponds to addresses
A27-A24, the second to A23-A20, until the seventh incoming nibble, which corresponds to addresses A3-A0. Incoming nib-
ble number eight is ignored. The MS bits of the 32-bit addresses are ‘1111’ (A31 - A28).
Core Interrupt
Whenever there is an LPC or FWH transaction that is responded to by any of the PC87591x logical devices, a positive pulse
is generated on the Host Access Wake-Up input of the MIWU module. This interrupt may be used to wake up the core for
handling any host activity.
CLKRUN Functionality
The PC87591x supports the CLKRUN I/O signal, the use of which is highly recommended in portable systems. This signal
is implemented according to the specification in PCI Mobile Design Guide, Revision 1.1, December 18, 1998. The PC87591x
supports operation with both a slow and stopped clock in ACPI state S0 (the system is active but is not being accessed).
The PC87591x drives the CLKRUN low to force the LPC bus clock into full speed operation when an IRQ is pending inter-
nally and waiting to be sent through the serial IRQ.
LPCPD Functionality
The PC87591x supports the LPCPD input. This signal is used when the V
LPC bus. The LPCPD signal conforms with Intel’s LPC Interface Specification, Revision 1.0. Note that if the PC87591x pow-
er supply exists while LPCPD is active, it is not mandatory to reset the PC87591x when LPCPD is de-asserted.
6.1.8
This section describes the SuperI/O configuration and ID registers (those registers with first level indexes in the range of
20
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
FWH Write Cycle:
16
page 351).
- 2E
SuperI/O Configuration Registers
16
). See Table 55 for a summary and directory of these registers.
22
16
Index
16
20
21
25
26
27
28
29
- 24
(0xE).
16
16
16
16
16
16
16
16
SID
SIOCF1
Reserved exclusively for National use
SIOCF5
SIOCF6
SRID
SIOCF8
SIOCF9
Mnemonic
Table 55. SuperI/O Configuration Registers
SuperI/O ID
SuperI/O Configuration 1
SuperI/O Configuration 5
SuperI/O Configuration 6
SuperI/O Revision ID
SuperI/O Configuration 8
SuperI/O Configuration 9
Register Name
343
(Continued)
DD
chip supply is not shared by all residents of the
Power Well
V
V
V
V
V
V
V
DD
DD
DD
DD
DD
DD
DD
Varies per bit
Type
R/W
R/W
R/W
R/W
RO
RO
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