pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 140

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
Timer Mode Control Register (TnCTRL)
The TnCTRL register is a byte-wide read/write register. It defines the mode of operation of timer/counter and TAn and TBn
I/O pins. The register is cleared on reset.
Location: MFT16 1: 00 FD8C
Type:
Bit
Name
Reset
1-0
Bit
2
3
4
5
6
7
MDSEL (Mode Select). Defines the MFT16 mode of operation.
Bits
1 0
0 0:
0 1:
1 0:
1 1:
TAEDG (TAn Edge Polarity).
0: A high-to-low transition on TAn causes the action defined by the mode of operation, e.g., input capture (default)
1: A low-to-high transition on TAn results in the defined action.
TBEDG (TBn Edge Polarity).
0: A high-to-low transition on TBn causes the action defined by the mode of operation, e.g., input capture or ex-
1: A low-to-high transition on TBn results in the defined action
In Pulse Accumulate mode, when this bit is set to 1, the count is enabled if TBn is high. When cleared (0) and
while operating in Pulse Accumulate mode, the counter is enabled if TBn is low.
TAEN (TAn Enable). Enables TAn to function either as a preset input or as a PWM output, depending on the
mode of operation.
If this bit is set (1), while operating in Dual Input Capture mode (mode 2), a transition on TAn causes TnCNT1
to be preset to FFFF
output. See Table 19 on page 137 for additional information.
TBEN (TBn Enable). When set (1), and while operating in either Dual Input Capture mode (mode 2) or Input
Capture and Timer mode (mode 4), a transition on TBn causes the corresponding timer/counter to be preset to
FFFF
while operating in any mode other than modes 2 or 4. See Table 19 on page 137 for additional information.
TAOUT (TAn Output Data). Contains the value of TAn output when TAn is used as a PWM output.
0: TAn is low (default)
1: TAn is high
This bit is set and cleared by hardware and thus reflects the status of TAn. This bit can be read at any time. It
may be used to set the initial value of TAn output in PWM mode. Note that if the hardware attempts to toggle
this bit at the same time as software is writing to the bit, the software write takes precedence over the hardware
update. This bit has no effect when TAn is used as input.
Reserved (must be set to 1).
MFT16 2: 00 FDAC
R/W
ternal event count (default)
16
(must be 1)
Reserved
. In mode 2, TnCNT1 is preset to FFFF
Description
Mode 1 (default)
Mode 2
Mode 3
Mode 4
7
0
16
16
16
TAOUT
. In the remaining modes of operation, setting TnAEN enables TAn to function as a PWM
6
0
TBEN
5
0
(Continued)
16
; in mode 4, TnCNT2 is preset to FFFF
TAEN
Description
140
4
0
TBEDG
3
0
TAEDG
2
0
16
. The bit has no effect
1
0
MDSEL
0
0
Revision 1.2