pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 157

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Status Register (UnSTAT)
This byte-wide, read-only register contains the receive and transmit status bits. The register is cleared (00
Location: USART1 - 00 FD26
Type:
Bit
Name
Reset
Bit
0
1
2
3
4
5
6
7
PE. The bit is set when a parity error is detected within a received character. The bit is cleared by the hardware
when UnSTAT register is read.
0: No parity error detected (default)
1: Parity error detected in a received byte since the last time UnSTAT was read
FE. The bit is set when the USART fails to receive a valid stop bit at the end of a frame. Automatically cleared
on read of UnSTAT.
0: No framing error detected (default)
1: Framing error detected on a received byte since the last time UnSTAT was read
DOE. The bit is set when a new character is received and transferred to RBUF before the software has read the
previous character. Automatically cleared on read of the UnSTAT.
0: No data overrun error detected (default)
1: Data overrun error detected since the last time UnSTAT was read
ERR. The bit is set any time DOE, FE or PE is set. Automatically cleared if DOE, FE and PE are all zero. This
bit is read only. Any attempt to write to the bit by software does not alter its present value.
0: No DOE, FE or PE has occurred since the last time UnSTAT register was read (default)
1: A DOE, FE or PE error has occurred since the last time UnSTAT register was read
BKD. If set, indicates that a line break condition has occurred. A break condition is detected if RXDn remains
low for a least ten bit times after a missing stop bit has been detected at the end of a frame. The bit is cleared
under the following conditions:
– On a read of UnSTAT register, if the break condition on RXDn is no longer present. If RXDn is still low when
– If the read of UnSTAT register did not cause the bit to be cleared because the break condition on RXDn was
RB9. Contains the ninth data bit of the last frame received when operating with the 9-bit data format.
0: ‘0’ received in ninth bit position (default)
1: ‘1’ received in ninth bit position
XMIP. Indicates that the USART is transmitting data. It is reset by hardware at the end of the last frame bit.
0: USART is not transmitting (default)
1: USART is transmitting
Reserved.
USART2 - 00 FC26
RO
UnSTAT register is read, the bit is not cleared.
still in effect, the hardware clears the bit as soon as the break condition no longer exists, i.e., RXDn returns to
a high level.
Reserved
7
0
16
16
XMIP
6
0
RB9
5
0
(Continued)
BKD
Description
157
4
0
ERR
3
0
DOE
2
0
FE
1
0
16
) on reset.
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PE
0
0