pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 222

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

4.0 Embedded Controller Modules
(Continued)
4.19.3 Debugger Interface Functional Description
The Debugger interface supports four operating modes: Rx session, Tx session, chip RESET and ABORT. Some of these
modes can be active simultaneously for the same or different processors. The ISE interrupt control block includes hooks to
control these conditions.
Rx Session (Sending Data Downstream)
A message sent downstream by the debugger to a processor is called an Rx session. In an Rx session, a debugger uses
both the TAP and the JTAG to monitor the “busy” indication for the Rx data link. Following a “not busy” indication, a message
is sent to a processor via the JTAG, TAP and Rx data link.
One of the internal ISE interrupts is asserted (if not active) according to the PID field of the instruction currently loaded into
the TAP IR register. The signaled processor accesses the data link via the peripheral bus, reads the message length (op-
tional) and fetches it from the Rx data buffer.
At the end of the data transfer, the processor turns off the “busy” indication of the Rx data link.
Tx Session (Sending Data Upstream)
A message sent upstream by a processor to the debugger is called a Tx session. In a Tx session, one of the processors
tries to own the Tx data link by accessing the Tx semaphore DBGTXLOC register. If successful, it writes a message body
to the Tx data buffer and a message length, in words, to DBGTXST register.
After completion of the data buffer update, the processor sets ASSERT bit in DBGTINT register to 1. This signals the de-
bugger with an active-low pulse on TINT. The debugger reads the data using both the TAP and the JTAG.
At the end of the data transfer, the semaphore circuit is set to “not busy” and TINT is released.
Chip RESET
The PC87591L-N05 is reset by a dedicated TAP instruction.
ABORT
Either a TAP instruction or a bit-set operation in DBGABORT register generates an ABORT. Asserting an ISE interrupt to-
gether with a non-zero ABORT_i bit in DBGISESRC register signals an ABORT operation. The ISE interrupt control circuit
asserts the ISE interrupt according to the pre-programed mask bits in ABORT_MASK register. A dedicated circuit, together
with a set of registers in the ISE Interrupt Control, clears the ISE requests after they have been served.
Rx Data Link
The Rx data link consists of an 8-word read/write data buffer, DBGRXD0 to DBGRXD7 registers and the Status (DBGRXST)
register.
On PC87591L-N05 reset, DBGRXST register is set to its reset value. On TAP reset, the data link maintains its values.
When the TAP controller is in Update-DR state and the current IR is SCAN_RX, DBGRXDX registers are updated from the
TAP Data Shift (DBGDATA) register. Data is valid to the processor only while BUSY bit in DBGRXST register is set. In this
case (i.e., Update-DR of SCAN_RX), the TAP controller copies the PID and length fields from its IR to the Status register
and sets BUSY bit to 1 in this state.
A processor may turn off the BUSY bit by writing 1 to it. BUSY can be cleared even when TCK is not toggling. The Rx data
link functions in Active or Idle modes.
DBGDATA length is set to the length field of the SCAN_RX instruction before Capture_DR state (see Section 4.19.6 on
page 229). No parallel load is executed in Capture-DR state.
Tx Data Link
The Tx Data link consists of an 8-word, read/write data buffer, DBGTXD0 to DBGTXD7 registers, a read/write Status register
(DBGTXST), a read/write semaphore lock register (DBGTXLOC) and a write-only TINT control register (DBGTINT).
On Power-Up reset, the Tx Data link is reset (negating any pending message), DBGTXLOC and DBGTXST are set to their
reset values and TINT is released (1). On Warm and Internal reset, any partial message (i.e., TINT=1) is negated by setting
DBGTXLOC and DBGTXST to their reset values. Messages that were completed (i.e., TINT=0) are maintained for transmis-
sion to the host by maintaining DBGTXLOC and DBGTXST values.
On TAP reset, the data link maintain its values.
DBGTXD registers are captured by the TAP data shift register (DBGDATA) in Capture-DR state of the TAP controller when
the current Information Register (IR) is SCAN_TX. The DBGDATA length is set dynamically, according to the length field of
DBGTXST register before the Capture_DR state of the SCAN_TX operation (see Section 4.19.6 on page 229). The TAP IR
register captures the values of PID and MSG_LEN fields of DBGTXST register when the TAP controller is in Capture-IR
state. No parallel load is executed in Update-DR state.
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