pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 267
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pc87591l-n05
Manufacturer Part Number
pc87591l-n05
Description
Lpc Mobile Embedded Controller
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L-N05.pdf
(401 pages)
- Current page: 267 of 401
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Revision 1.2
5.0 Host Controller Interface Modules
The Shared Memory Core Override Read Protect 0-2 registers and Shared Memory Core Override Write Protect 0-2 regis-
ters provide core access to the read and write protect bits, respectively. Bits in these registers may be set and cleared by
writing to the registers.
Response to a Restricted Access
A restricted access is an access that complies with at least one of the following conditions:
The PC87591L-N05 responds to a restricted access by generating an interrupt (if enabled by HERRIEN bit in SMCCST reg-
ister) to the core. Two status bits (HWERR and HRERR) indicate whether the restricted access is a read or write access.
The response on the host bus is according to the HERES field.
For restricted write accesses: Data written is ignored; when the HERES field is 10
with an error SYNC; otherwise, it is completed with a ready SYNC.
For restricted read accesses: When the HERES field is 00
access becomes unrestricted or the HERES field is changed). When the field is 01
action with a ready SYNC and data of 00
00
• The access type (i.e., Read or Write) of the translated host address (i.e., core address) is protected.
• A reset to the core domain due to a Warm reset event is set (Core Boot Block field of PTWRL register is 1111
16
.
Host Block
Figure 93. Protection Blocks for Protection Bits and Override Protection Bits
Index
17
16
15
3
2
1
0
31
Core Address
Address in
00 E000
0F 0000
12 0000
11 0000
10 0000
04 0000
03 0000
02 0000
01 0000
00 0000
1F FFFF
1F 0000
Space
16
; when the field is 10
~ ~
64K
64K
(Continued)
2
, the read or write transaction drives Long Wait (endlessly, unless the
64K
64K
64K
64K
64K
64K
267
8K
8K
8K
8K
8K
8K
8K
2
, it completes the transaction with an error SYNC and data of
~ ~
~ ~
Core Override
Block Number
~ ~
LA 15
LA 8
LA 6
LA 2
LA 1
LA 0
31
17
16
15
3
2
2
2
, the read or write transaction is completed
, the PC87591L-N05 completes the trans-
MBTA
Area Not Accessible
to Host
www.national.com
2
).
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