pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 292

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Module
MSWC Control Status Register 2 (MSWCTL2)
This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. Bits in this register
are cleared by V
Location: 00 FCC2
Type:
Bit
Name
Reset
5-1 R/W1C ACPIS1-5 (ACPI request for S1 through S5). These bits may be used by ACPI software to directly
Bit
7-6
0
6
7
Bit
4
5
R/W1C ACPIS0 (ACPI request for S0). This bit may be used by ACPI software to directly request a change of
R/W1C CFGPSO (SuperI/O Configuration Register D Power Supply Off). This bit is set whenever a 1 is
Type
RO
R/W1S HCFGLK (Host Configuration Address Lock). This bit is cleared during V
R/W1C HSECM (Host Software Event Clear Mode). Controls the clear mode of Host Software Event Status
Varies per bit
Type
CFGPSO
power state. This bit is set when the host software writes a value of 0 to bits S1 through S5 in
WK_STATE register. This bit is cleared by writing 1 to it. A write of 0 is ignored.
When ACPIS0 is set, an MSWC wake-up interrupt to the core, is asserted (via a MIWU input).
0: No pending request for S0 change (default)
1: A request for S0 change was detected
request a change of power state. These bits are set by a host software write of 1 to the respective bit in
WK_STATE register. The bit is cleared by writing 1 to it. A write of 0 is ignored.
When any ACPIS1-5 bit is set, an MSWC wake-up interrupt to the core is asserted (via a MIWU input).
CFGPBM (SuperI/O Configuration Register D Power Button Mode). This bit reflects the current
status of the Power Button Mode bit in SIOCFD register. This bit may be used by the host software to
specify to the core the method used for power off signaling. See “SuperI/O Configuration D Register
(SIOCFD)” on page 309
A write of 1 clears the interrupt signal caused by a change in this bit value. A write of 0 to this bit is
ignored.
written to the Power Supply Off bit in SIOCFD register. This bit may be used by the host software to
specify to the core that the power supply should be turned off in a non-ACPI system. See “SuperI/O
Configuration D Register (SIOCFD)” on page 309.
A write of 1 clears this bit and the interrupt signal generated when this bit is set. A write of 0 to this bit
is ignored.
CC
reset or Debugger Interface reset, but is unchanged during other reset events.
When 1 is written to this bit, it becomes read only (i.e., it cannot be cleared by the firmware) and
locks VHCFGA bit, HCFGBAH register and HCFGBAL register, preventing accidental alteration to
them.
0: Allows update of the Host Configuration Registers base address (default)
1: Locks the Host Configuration Registers base address
bit in WK_STS0. This bit is cleared at V
0: Host Software Event Status bit in WK_STS0 (bit 6) toggles on host writes of 1. MSHES0 bit 6 is set
1: Host Software Event Status bit in WK_STS0 (bit 6) and MSHES0 bit 6 are both cleared by writes of
Reserved.
Power-Up and RESET1 resets.
16
7
0
when WK_STS0 bit 6 changes from 0 to 1 (default).
1 to MSHES0 register
CFGPBM
6
0
ACPIS5
5
0
(Continued)
ACPIS4
292
CC
4
0
Description
power-up and RESET1 events.
Description
ACPIS3
3
0
ACPIS2
2
0
CC
ACPIS1
power-up, Watchdog
1
0
ACPIS0
0
0
Revision 1.2