pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 144

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
4.8.3
The PWM module supports duty cycles in the range of 0% to 100%.
The PWMi output signal cycle time is: (PRSC + 1) x (CTR + 1) x T
where:
The PWMi output signal duty cycle (in %, when INVPi is 0) is: (DCRi + 1) / (CTR + 1) x 100.
Special cases:
When Inverse PWMi bit is 1, the value of PWMi output is inverted. i.e., in the period described as 1 is 0 and vice versa.
4.8.4
The PWM is in Low Power mode when Power Mode bit (PWR) in PWM Control Register (PWMCNT) is 0. In this mode, the
PWM input clock is disabled (stopped), but the registers are accessible and maintained. The PWMi signal is 0 when INVPi
bit is 0; it is 1 when INVPi bit is 1.
The PWM is in normal power mode when PWR bit in PWMCNT register is 1. In this mode, the PWM module is enabled, its
registers are accessible and its clock is functional.
The PRSC and CTR registers should be updated during Low Power mode. Otherwise, there may be unpredictable transient
behavior.
4.8.5
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 32.
PWM Register Map
Clock Pre-Scaler Register (PRSC)
The PRSC register controls the cycle time and the minimal pulse width. PRSC is cleared (0000
Location: 00 FD00
Type:
• T
• The cycle time may range from 2 x T
• If the DCRi value is greater than the CTR value, PWMi signal is always low.
• If DCRi value is equal to the CTR value, PWMi signal is always high.
Bit
Name
Reset
15-0 Pre-Scaler Divider Value. The divider of the Input Clock is the number defined either by PRSC15-0 + 1 when
Bit
CLK
Cycle Time and Duty Cycle Calculation
Power Modes
PWM Registers
PWMRES bit (in PWMCNT register) is set to 1, or by PRSC7-0 + 1 when PWMRES bit is set to 0. For example,
a value of 0000
When PWMRES bit is set to 0, only the low byte (PRSC7-0) of this register must be written (PRSC15-8 are ignored).
The contents of this register may be changed only when the PWM module is in Low Power mode. Otherwise,
there may be unpredictable results.
is the core domain clock cycle time (i.e., the PWM input clock).
R/W
15
0
16
PRSC
CTR
DCRi
PWMPOL
PWMCNT
Mnemonic
14
0
16
results in a divide by 1, a value of FFFF
13
0
12
Clock Pre-Scaler
Cycle Time
Duty Cycle 0 to 7
PWM Polarity
PWM Control
0
CLK
11
0
to 65536 x T
(Continued)
10
0
Register Name
9
0
CLK
Description
144
.
PRSC15-0
8
0
CLK
16
7
0
results in a divide by 65536.
6
0
5
0
Type
R/W
R/W
R/W
R/W
R/W
4
0
16
) on reset.
3
0
2
0
1
0
Revision 1.2
0
0