pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 141

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
4.0 Embedded Controller Modules
Timer Interrupt Control Register (TnICTL)
The TnICTL register is a byte-wide read/write register. It contains the interrupt enable bit and associated interrupt pending
bits for the four timer interrupt sources. The TnICTL register format is shown below. The register is cleared on reset.
Location: MFT16 1: 00 FD8E
Type:
Bit
Name
Reset
Bit
0
1
2
3
4
5
6
7
TAPND (Timer Interrupt Source A Pending). When asserted, indicates that an interrupt condition (as shown
in Table 18 on page 136) has occurred. This bit can be set by either hardware or software.
This bit can not be cleared (set to 0) directly. TAPND can be cleared via the Timer Interrupt Clear register.
A write of 0 to TAPND is ignored. The bit is cleared on reset.
Timer Interrupt Source B Pending (TBPND). Same as TAPND but for a different condition, as shown in
Table 18.
Timer Interrupt Source C Pending (TCPND). Same as TAPND but for a different condition, as shown in
Table 18.
Timer Interrupt Source D Pending (TDPND). Same as TAPND but for a different condition, as shown in
Table 18.
TAIEN (Timer Interrupt A Enable).
0: No system interrupt occurs, but the associated pending flag TAPND is set
1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 18
Note: The bit can be set or cleared by software at any time.
TBIEN (Timer Interrupt B Enable).
0: No system interrupt occurs, but the associated pending flag TBPND is set (default)
1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 18
Note: The bit can be set or cleared by software at any time.
TCIEN (Timer Interrupt C Enable).
0: No system interrupt occurs, but the associated pending flag TCPND is set (default)
1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 18
Note: The bit can be set or cleared by software at any time.
TDIEN (Timer Interrupt D Enable).
0: No system interrupt occurs, but the associated pending flag TDPND is set (default)
1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 18
Note: The bit can be set or cleared by software at any time.
MFT16 2: 00 FDAE
R/W
TDIEN
7
0
16
16
TCIEN
6
0
TBIEN
5
0
(Continued)
TAIEN
Description
141
4
0
TDPND
3
0
TCPND
2
0
TBPND
1
0
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TAPND
0
0