pc87591l-n05 National Semiconductor Corporation, pc87591l-n05 Datasheet - Page 243

• Manufacturer Part Number: pc87591l-n05
• Description: Lpc Mobile Embedded Controller
• Manufacturer: National Semiconductor Corporation

Revision 1.2
5.0 Host Controller Interface Modules
The Host configuration module assigns host interrupts to IRQ numbers (see Section 6.1.10 on page 310). These interrupts
are IRQ1 and IRQ12 for keyboard and mouse IRQs, respectively.
When IRQ1 and/or IRQ12 are disabled (OBFKIE and/or OBFMIE bits in HICTRL register are cleared), the firmware can con-
trol the IRQ1 and/or IRQ12 signals by writing to the signal’s respective bit in HIIRQC register.
When IRQ1 and/or IRQ12 are controlled by hardware (OBFKIE and/or OBFMIE bits in HICTRL register are set to 1), inter-
rupts to the host are generated according to the status of Output Buffer Full (OBF) flag.
In normal polarity mode (IRQNPOL in HIIRQC register is set to 0), the PC87591L-N05 supports two types of interrupts: Leg-
acy Edge and Level. When an Edge interrupt is selected (IRQM in HIIRQC register is set), the interrupt signal default value
is high (1). When an interrupt signal must be sent (i.e., the corresponding OBF flag is set), a negative pulse is generated.
The pulse width is determined by IRQM field in HIIRQC register.
When the IRQ signals are set as level interrupts (IRQM in HIIRQC register is set to 0), the interrupt signal is usually low (0)
and is asserted (1) to indicate that the respective OBF flag is set. The signal is de-asserted (0) when the output buffer is read
(i.e., OBF flag is cleared).
Note that IRQ1 and IRQ12 have the same OBF flag but are not asserted together. Either IRQ1 or IRQ12 is set, depending
on the internal register written (HIKDO or HIMDO, respectively).
In negative polarity mode (IRQNPOL in HIIRQC register is set to1), the IRQ signal behavior is inverted from the behavior
described above.
The PC87591L-N05 firmware can read the values of the IRQ1 and IRQ12 signals by performing a read operation from IRQ1B
and IRQ12B bits in HIIRQC register.
Figure 84 shows the effect of the different control bits on the IRQ signals.
Keyboard/Mouse Channel (60
The Host Interface of the PC87591L-N05 is compatible with the legacy 8042 host interface. It is based on two registers: Com-
mand/Data and Status. The Host Interface logic generates interrupts to the host processor and core according to the status
of the input and output data buffers. Figure 85 provides a schematic description of the Host Interface Keyboard/Mouse chan-
nel.
IRQxB bit (HIIRQC)
IRQxB bit (HIIRQC)
IRQM field (HIIRQ)
(write)
Hardware
Interrupt
(read)
Figure 84. IRQx (IRQ1, IRQ11 or IRQ12) Control Diagram
16
IRQxB bit (HIIRQC)
, 64
16
IRQNPOL bit (HIIRQC)
)
1
0
(Continued)
243
OBFMIE or OBFKIE bit
(HICTRL)
1
0
(Part of SuperI/O
IRQ Serializer
Configuration
IRQ Routing
and Polarity
Module)
www.national.com
Serializer
IRQ