m41st87w STMicroelectronics, m41st87w Datasheet - Page 11

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m41st87w

Manufacturer Part Number
m41st87w
Description
5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
Manufacturer
STMicroelectronics
Datasheet

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Figure 8. Bus Timing Requirements Sequence
Table 2. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
t
Symbol
HD:DAT
t
t
t
t
SU:STO
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
HD:STA
SU:DAT
SU:STA
t
t
t
EXPD
f
t
HIGH
LOW
SCL
BUF
t
t
R
F
SDA
SCL
(2)
tBUF
SCL Clock Frequency
Time the bus must be free before a new transmission can start
EX to E
SDA and SCL Fall Time
Data Hold Time
START Condition Hold Time
(after this period the first clock pulse is generated)
Clock High Period
Clock Low Period
SDA and SCL Rise Time
Data Setup Time
START Condition Setup Time
(only relevant for a repeated start condition)
STOP Condition Setup Time
P
CON
Propagation Delay
S
tHD:STA
tR
A
tLOW
Parameter
tHIGH
= –40 to 85°C; V
tF
(1)
tHD:DAT
CC
= 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
tSU:DAT
M41ST87W
M41ST87Y
SR
tSU:STA
M41ST87Y, M41ST87W
tHD:STA
Min
600
600
100
600
600
1.3
1.3
0
0
P
AI00589
tSU:STO
Max
400
300
300
10
15
Unit
kHz
11/42
µs
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns

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