m41st87w STMicroelectronics, m41st87w Datasheet - Page 32

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

M41ST87Y, M41ST87W
Power-fail Comparators (1 and 2)
Two Power-Fail Inputs (PFI
pared to an internal reference voltage (1.25V). If
either PFI
threshold (V
(PFO
ed for use as an under-voltage detector to signal a
failing power supply. Typically PFI
connected through external voltage dividers (see
Figure 5., page
put (if it is available) or the regulated output of the
V
such that the voltage at PFI
V
V
sor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO
This occurs after V
When power returns, PFO
high, irrespective of V
(t
puts are recognized. At the end of this time, the
power-fail comparator is enabled and PFO
PFO
unused, PFI
and the associated PFO
ed.
Power-fail Outputs
The PFO
as N-channel, open drain output drivers, or full-
CMOS output drivers. By setting the Power-fail
Output Open Drain Bit (PFOD) to a '1,' the output
will be configured as open drain (with I
ified in
'0,' the outputs will be configured as full-CMOS
(sink and source current as specified in
17., page
Note: When configured as open drain (PFOD =
'1'), PFO
up resistor.
Century Bits
These two bits will increment in a binary fashion at
the turn of the century, and handle leap years cor-
rectly. See
nation.
Output Driver Pin
When the TIE Bit, OFIE Bit, AFE Bit, and watch-
dog register are not set to generate an interrupt,
the IRQ/OUT pin becomes an output driver that re-
32/42
rec
CC
PFI
CC
), which is the time from V
input to the M41ST87Y/W or the microproces-
2
regulator. The voltage divider can be set up
1
several milliseconds before the regulated
follow PFI
or PFO
Table 17., page
1
1
37).
1
and PFO
Table 11., page 33
and PFO
PFI
1
or PFI
or PFI
2
), the associated Power-Fail Output
) will go low. This function is intend-
8) to either the unregulated DC in-
1
1
and PFI
2
and PFO
2
2
2
CC
should be connected to V
will require an external pull-
is less than the power-fail
PFI
outputs are programmable
37). When PFOD is set to
1
drops below V
for the write protect time
or PFO
1
2
1
. If the comparator is
and PFO
1
2
PFD
and PFI
for additional expla-
or PFI
go (or remain) low.
(max) until the in-
2
1
left unconnect-
and PFI
2
2
2
OL
falls below
) are com-
are forced
PFD
as spec-
(min).
1
Table
2
and
are
SS
flects the contents of D7 of the Control Register. In
other words, when D7 (OUT Bit) is a '0,' then the
IRQ/OUT pin will be driven low. With the ABE Bit
set to '1,' the OUT pin will continue to be driven low
in battery back-up.
Note: The IRQ/OUT pin is an open drain which re-
quires an external pull-up resistor.
Battery Low Warning
The M41ST87Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The battery may be re-
placed while V
The M41ST87Y/W only monitors the battery when
a nominal V
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
t
Bit D7 of Clock Register 04h contains the t
(TR). t
the deselect time after V
lows for a voltage settling time before WRITEs
may again be performed to the device after a pow-
er-down condition. The t
set the length of this deselect time as defined by
Table 12., page
rec
Bit
rec
refers to the automatic continuation of
CC
CC
is applied to the device. Thus appli-
33.
is applied to the device.
rec
CC
Bit will allow the user to
reaches V
PFD
. This al-
rec
CC
Bit
is