m41st87w STMicroelectronics, m41st87w Datasheet - Page 15

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

Data Retention Mode
With valid V
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST87Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when V
V
18., page
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until V
External RAM access is inhibited in a similar man-
ner by forcing E
within 0.2 volts of the V
this level as long as V
erance condition. When V
tery Back-up Switchover Voltage (V
input is switched from the V
and the clock registers and external SRAM are
maintained from the attached battery supply.
All outputs become high impedance. The V
is capable of supplying 100µA (for M41ST87W) or
150µA (for M41ST87Y) of current to the attached
memory with less than 0.3 volts drop under this
condition. On power up, when V
nominal value, write protection continues for t
by inhibiting E
active during this time (see
Note: Most low power SRAMs on the market to-
day can be used with the M41ST87Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST87Y/W and SRAMs to be “Don’t Care”
once V
should also guarantee data retention down to
V
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to V
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
PFD
CC
=2.0 volts. The chip enable access time must
(min) (see
CC
CC
38). This is accomplished by internally
CC
falls below V
falls between V
CON
applied, the M41ST87Y/W can be
CON
. The RST signal also remains
Figure
CC
to a high level. This level is
CC
returns to nominal levels.
BAT
remains at an out-of-tol-
CC
OUT
PFD
Figure 28., page
28., page
. E
CC
falls below the Bat-
(min). The SRAM
.
CON
pin to the battery,
PFD
CC
will remain at
returns to a
(max) and
38,
SO
), power
OUT
Table
38).
pin
rec
the SRAMs can then be added to the I
the M41ST87Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the battery of your choice can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Tamper Detection Circuit
The M41ST87Y/W provides two independent in-
put pins, the Tamper Pin 1 Input (TP1
Tamper Pin 2 Input (TP2
monitor two separate signals which can result in
the associated setting of the Tamper Bits (TB1
and/or TB2, in Flag Register 0Fh) if the Tamper
Enable Bits (TEB1 and/or TEB2) are enabled, for
the respective Tamper 1 or Tamper 2. The TP1
Pin or TP2
event has occurred by either 1) closing a switch to
ground or V
a switch that was previously closed to ground or
V
of the TCM
Register (14h and/or 15h).
Tamper Register Bits (Tamper 1 and Tamper 2)
Tamper Enable Bits (TEB1 and TEB2). When
set to a logic '1,' this bit will enable the Tamper De-
tection Circuit. This bit must be set to '0' in order to
clear the associated Tamper Bits (TB
Note: TEB
Detect condition is modified.
Tamper Bits (TB1 and TB2). If the TEB
set, and a tamper condition occurs, the TB
be set to '1.' This bit is “Read-only” and is reset
only by setting the TEB
located in the Flags Register 0Fh.
Tamper Interrupt Enable Bits (TIE1 and TIE2).
If this bit is set to a logic '1,' the IRQ/OUT pin will
be activated when a tamper event occurs. This
function is also valid in battery back-up if the ABE
Bit (Alarm in Battery Back-up) is also set to '1' (see
Figure 15., page
Note: In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to reset-
ting the TEB
OUT
(Normally Closed), depending on the state
X
IN
X
OUT
should be reset whenever the Tamper
X
Bits and the TPM
Pin may be set to indicate a tamper
Bit.
(Normally Open), or by 2) opening
17).
M41ST87Y, M41ST87W
X
IN
Bit to '0.' These bits are
), which can be used to
X
Bits in the Tamper
X
BAT
, in 0Fh).
X
value of
X
IN
Bit will
) and
Bit is
15/42
IN