m41st87w STMicroelectronics, m41st87w Datasheet - Page 23

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

Avoiding Inadvertent Tampers (Normally
Closed Configuration)
In some applications it may be necessary to use a
low pass filter to reduce electrical noise on the
Tamper Input pin when the TCM
Closed). This is especially true if the tamper detect
switch is located some distance (> 6”) from the
Tamper Input pin. A low pass filter can prevent un-
wanted, higher frequency noise from inadvertently
being detected as a tamper condition caused by
the “antenna-effect” (produced by a longer signal
wire or mesh). This low pass filter can be con-
structed using a series resistor (R) in conjunction
with a capacitor (C) on the Tamper Input pin.
The cut-off frequency f
the formula:
Table 6. Calculated Cut-off Frequency for Typical Capacitance and Resistance Values
Tamper Event Time-Stamp
Regardless of which tamper occurs first, not only
will the appropriate Tamper Bit be set, but the
event will also be automatically time-stamped.
This is accomplished by freezing the normal up-
date of the clock registers (00h through 07h) im-
mediately following a tamper event. Thus, when
tampering occurs, the user may first read the time
registers to determine exactly when the tamper
event occurred, then re-enable the clock update to
the current time (and reset the Tamper Bit, TB
resetting the Tamper Enable Bit (TEB
The time update will then resume and the clock
can be read to determine the current time. Both
Tamper Enable Bits (TEB
'0' in order to read the current time.
10000
10000
R ( )
1000
1000
5000
5000
f c
=
1
c
2 Pi R C
is determined according to
X
) must always be set to
X
Bit = 0 (Normally
1.00E-09
1.00E-06
1.00E-09
1.00E-06
1.00E-09
1.00E-06
C (F)
X
).
X
) by
Figure 21. Low Pass Filter Implementation for
Noise Immunity
In the event of multiple tampers, the Time-Stamp
will reflect the initial tamper event.
Note: If the TEB
Time-Stamp will take precedence over the Power
Down Time-Stamp (see
Stamp, page
not be set during the power-down event. If both
are needed, the Power Down Time-Stamp may be
accomplished by writing the time into the General
Purpose RAM memory space when PFO is assert-
ed.
To Tamper Detect Switch
15.9MHz
159.2Hz
31.8kHz
15.9kHz
31.8Hz
15.9Hz
f
c
24) and the HT Bit (Halt Update) will
X
Bit is set, the Tamper Event
M41ST87Y, M41ST87W
Power-Down Time-
R
6.28ms
31.4ms
62.8ms
1/f
6.28µs
31.4µs
62.8µs
c
C
(s)
AI11185
TP IN
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