m41st87w STMicroelectronics, m41st87w Datasheet - Page 14

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

M41ST87Y, M41ST87W
WRITE Mode
In this mode the master transmitter transmits to
the M41ST87Y/W slave receiver. Bus protocol is
shown in
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
Figure 12. WRITE Mode Sequence
Figure 13. WRITE Cycle Timing: RTC & External SRAM Control Signals
14/42
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
EX
E CON
Figure 12., page
S
ADDRESS
SLAVE
14. Following the
tEXPD
ADDRESS (An)
WORD
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST87Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see
9., page
word address and each data byte.
DATA n
tEXPD
12) and again after it has received the
DATA n+1
DATA n+X
AI00591
AI03663
P
Figure