m41st87w STMicroelectronics, m41st87w Datasheet - Page 9

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

OPERATING MODES
The M41ST87Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 160 bytes con-
tained in the device can then be accessed sequen-
tially in the following order:
00h.
01h.
02h.
03h.
04h.
05h.
06h.
07h.
08h.
09h.
0Ah-0Eh. Alarm Registers
0Fh.
10h-12h. Reserved
13h.
14h.
15h.
16h-1Dh. Serial Number (8 bytes)
1Eh-1Fh. Reserved (2 bytes)
20h-9Fh. User RAM (128 bytes)
The M41ST87Y/W clock continually monitors V
for an out-of-tolerance condition. Should V
below V
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
CC
PFD
Tenths/Hundredths of a Second Regis-
ter
Seconds Register
Minutes Register
Century/Hours Register
Day Register
Date Register
Month Register
Year Register
Control Register
Watchdog Register
Flag Register
Square Wave
Tamper Register 1
Tamper Register 2
falls below V
, the device terminates an access in
SO
, the device automati-
CC
fall
CC
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
and the power supply is switched to external V
Write protection continues until V
(min) plus t
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
– During data transfer, the data line must remain
– Changes in the data line, while the clock line is
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
CC
is not busy.
stable whenever the clock line is High.
High, will be interpreted as control signals.
rises above V
rec
(min).
SO
, the battery is disconnected,
M41ST87Y, M41ST87W
CC
reaches V
9/42
PFD
CC
.