m41st87w STMicroelectronics, m41st87w Datasheet - Page 18

• Manufacturer Part Number: m41st87w
• Description: 5.0, 3.3, Or 3.0v, 1280 Bit 160 X8 Secure Serial Rtc And Nvram Supervisor With Tamper Detection
• Manufacturer: STMicroelectronics

M41ST87Y, M41ST87W
Tamper Detect Sampling (TDS1 and TDS2).
This bit selects between a 1Hz sampling rate or
constant monitoring of the Tamper Input Pin(s) to
detect a tamper event when the Normally Closed
switch mode is selected. This allows the user to re-
duce the current drain when the TEB
abled while the device is in battery backup (see
Table 4., page 18
pling is disabled if the TCM
(Normally Open). In this case the state of the
TDS
Note: The crystal oscillator must be “On” for sam-
pling to be enabled.
Tamper Current Hi/Tamper Current Lo (TCHI/
TCLO1 and TCHI/TCLO2). This bit selects the
strength of the internal pull-up or pull-down used
during the sampling of the Normally Closed condi-
tion. The state of the TCHI/TCLO
care” for Normally Open (TCM
Figure 18., page
RAM Clear (CLR1 and CLR2). When either of
these bits and the TEB
the internal 128 bytes of user RAM (see
15., page
event of a tamper condition. The 128 bytes of user
RAM will be deselected (invalid data will be read)
until the corresponding TEB
RAM Clear External (CLR1
When either of these bits are set to a logic '1' and
the TEB
SRAM will be cleared and the RST output enabled
(see
20., page
Note: The reset output resulting from a tamper
event will be the same as a reset resulting from a
power-down condition, a watchdog time-out, or a
manual reset (RSTIN1 or RSTIN2).
Table 4. Tamper Detection Current (Normally Closed - TCM
Note: 1. When calculating battery lifetime, this current should be added to I
18/42
TDS
X
2. Per Tamper Detect Input
Bit is a “Don’t care.”
0
0
1
1
X
X
Figure
17) will be cleared to all zeros in the
21).
Bit is also set to logic '1,' the external
TCHI/TCLO
19).
and
15., page 17
0
1
0
1
Figure 17., page
X
Bit are set to a logic '1,'
X
X
X
Continuous Monitoring / 10M
Continuous Monitoring / 1M
Sampling (1Hz) / 10M
Sampling (1Hz) / 1M
EXT
Bit is reset to '0.'
Bit is set to logic '1'
X
= '1') mode (see
X
and CLR2
and
Bit is a “Don’t
X
19). Sam-
Tamper Circuit Mode
Bit is en-
Figure
Figure
EXT
).
pull-up/-down
pull-up/-down
This is accomplished by forcing TP
if used to control the inhibit pin of the DC regulator
(see
depriving the external SRAM of power to the V
pin. V
the battery if the tamper occurs during battery
back-up (see
the DC regulator, the user will also prevent other
inputs from sourcing current to the external SRAM,
allowing it to retain data.
The user may optionally connect an inverting
charge pump to the V
(see
cess technology used for the manufacturing of the
external SRAM, clearing the memory may require
varying durations of negative potential on the V
pin. This device configuration will allow the user to
program the time needed for their particular appli-
cation. Control Bits CLRPW0 and CLRPW1 deter-
mine the duration TP
Figure 19., page 20
Note: When using the inverting charge pump, the
user must also provide isolation in the form of two
additional small-signal power MOSFETs. These
will isolate the V
voltage generated by the charge pump during a
tamper condition, and from being pulled to ground
by the output of the charge pump when it is in shut-
down mode (SHDN = logic low). The gates of both
MOSFETs should be connected to TP
shown in
hancement MOSFET should be placed between
the output of the inverting charge pump and the
V
be an enhancement mode p-channel, and placed
between V
ternal SRAM. When TP
tamper condition occurs, the n-channel MOSFET
will turn on and the p-channel will turn off. During
normal operating conditions, TP
and the p-channel will be on, while the n-channel
will be off.
pull-up/-down
OUT
pull-up/-down
BAT
Figure 20., page
Figure 20., page
current listed in
OUT
of the M41ST87. The other MOSFET should
X
Figure 20., page
will automatically be disconnected from
= '0')
OUT
Figure 19., page
of the M41ST87 and V
OUT
Table 17., page
Current at 3.0V (typ)
and
CC
21) will also switch off V
pin from both the negative
21). Depending on the pro-
CLR
Table 5., page
pin of the external SRAM
CLR
21. One n-channel en-
will be enabled (see
0.3
3.0
0.3
3.0
37.
goes high after a
20). By inhibiting
CLR
CLR
CC
(1,2)
will be low
high, which
20).
of the ex-
CLR
Unit
µA
µA
nA
nA
OUT
CC
CC
as
,