xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 12

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

Table 3: General Configuration Mode Timing Characteristics
Initialization
Upon power-up, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When V
age at which portions of the XCR3320 begin to operate
(1.5V), the configuration pins are set to be inputs or outputs
based on the configuration mode, as determined by the
mode select inputs M[2:0]. The mode pins must be stable
t
resetn. A time-out delay is initiated when V
between 1.0V and 2.0V to allow the power supply voltage
to stabilize. The done output is low. At power-up, if the
power supply does not rise from 1.0V to V
ms, the user should delay configuration by inputting a low
into prgmn or resetn until V
mended minimum operating voltage (3.0V for commercial
devices). If prgmn has a rise time of greater than one
microsecond, resetn must be held low until after prgmn
goes high. If the rise time for prgmn is 1 ms or less, the
order in which these pins go high is arbitrary.
The High During Configuration (hdc), Low During Configu-
ration (ldcn), and done signals are active outputs in the
XCR3320’s initialization and configuration states. hdc, ldcn,
and done can be used to provide control of external logic
signals such as reset, bus enable, or EEPROM enable dur-
ing configuration. For master parallel configuration mode,
these signals provide EEPROM enable control and allow
the data pins to be shared with user logic signals.
If configuration has begun, an assertion of resetn or prgmn
initiates an abort, returning the XCR3320 to the initializa-
DS033 (v1.3) October 9, 2000
All Configuration Modes
t
t
t
t
t
t
t
Master Modes
t
t
Slave Serial, Slave Parallel, And Synchronous Peripheral Modes
t
t
SMODE
SMODE
HMODE
PW
gtsr
IL
PORD
r
CCLK
CL
CCLK
CL
Symbol
nanoseconds before the rising edge of prgmn or
R
M[3:0] setup time to prgmn high
M[3:0] hold time from done high
prgmn pulse width low
Global 3-state disable
Initialization latency (prgmn high to hdc high)
XCR3320
Power-on reset delay
Configuration signal rise time
cclk period
Configuration latency (non-compressed)
XCR3320
cclk period
Configuration latency (non-compressed)
XCR3320
This product has been discontinued. Please see
CC
is greater than the recom-
CC
CC
reaches the volt-
in less than 25
Parameter
CC
reaches
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1-800-255-7778
tion state. The resetn and prgmn pins must be high before
the XCR3320 will enter the configuration state, and the
mode pins must be stable t
they rise. During the start-up and operating states, only the
assertion of prgmn causes a reconfiguration.
During initialization and configuration, all I/O’s are 3-stated
and the internal weak pull-downs are active. See
tions” on page 8
Start-up
After configuration, the XCR3320 enters the start-up
phase. This phase is the transition between the configura-
tion and operational states. This transition occurs within
three cclk cycles of the done pin going high (it is acceptable
to have additional cclk cycles beyond the three required).
The system design task in the start-up phase is to ensure
that multi-function pins
page
definable I/Os without inadvertently activating devices in
the system or causing bus contention. The done signal
goes High at the beginning of the start up phase, which
allows configuration sources to be disconnected so that
there is no bus contention when the I/Os become active. In
addition to controlling the XCR3320 during start-up, addi-
tional start-up techniques to avoid contention include using
isolation devices between the XCR3320 and other circuits
in the system, re-assigning I/O locations, and keeping I/Os
3-stated until contentions are resolved. For example,
Figure 10
nal to avoid signal contention when any multi-function pins
Single device
Single device
Daisy-chain
Daisy-chain
36.) transition from configuration signals to user
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M3 = 1
M3 = 1
M3 = 1
XCR3320: 320 Macrocell SRAM CPLD
shows how to use the Global 3-state (GTS) sig-
for more information.
(See “230-pin Function Table” on
1000
Min.
250
714
135
100
189
10
50
19
0
1
-
SMODE
nanoseconds before
Max.
1667
700
316
1.0
40
-
-
-
-
-
-
-
for details.
“Termina-
Unit
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
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