xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 41

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

This product has been discontinued. Please see
XCR3320: 320 Macrocell SRAM CPLD
160 Pin Description Table
Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.
Table 18: Pin Function Description
41
Symbol
resetn
prgmn
mpmi
GND
done
spmi
trstn
V
cclk
tms
din
M2
M0
M1
M3
tdo
tck
tdi
CC
15, 23, 40, 53,
62, 71, 80, 81,
47, 60, 64, 77,
113, 124, 137,
130, 139, 148
99, 106, 121,
8, 17, 24, 32,
Pin Number
89, 98, 104,
141, 154
159
157
158
160
110
108
151
46
63
95
42
44
41
43
97
5
Type
I/O
I/O
O
O
O
-
-
I
I
I
I
I
I
I
I
I
Positive power supply.
Ground supply.
During configuration, resetn forces the start of initialization. After configuration,
resetn is a direct input which can be used to asynchronously reset all the flip-flops. If
the global reset is not being used, this pin should be pulled High. If the rise time of
the prgmn signal is greater than 1 s, this signal must be held low until prgmn is High.
In the master modes, cclk is an output which strobes configuration data in. In the
slave or synchronous peripheral mode, cclk is an input synchronous with the data on
din or D[7:0]. After configuration, this pin should be pulled Low.
done is a bi-directional signal with a weak pull-up resistor attached. As an output,
done pulling High indicates configuration is complete. As an input, a Low level on
done will delay the enabling of user I/O. If only one device is used, this pin can be left
floating. If multiple devices are daisy chained, an external pull-up should be used.
prgmn is an active-low input that forces the restart of configuration and initialization
and resets the boundary-scan circuitry. After configuration, the pin should be pulled
high. This signal must have a rise time less than 1 microsecond. If the rise time of this
signal is greater than 1 microsecond, resetn must be held low until prgmn is high.
Special purpose configuration pin that must be left floating during configuration for all
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
Special purpose configuration pin that must be left floating during configuration for all
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
During slave serial or master serial configuration modes, din accepts serial
configuration data synchronous with cclk. During parallel configuration modes, din is
the D[0] input. After configuration, the pin is a user-programmable I/O, and no
external termination is required. See the section on terminations for more information.
M2/M1/M0 are used to select the configuration mode. After configuration, the pins are
user-programmable I/O, and no external termination is required. See
on page 8
M3 should be pulled high during configuration for all configuration modes. After
configuration, the pin is a user-programmable I/O, and no external termination is
required. See
Test Data In, Test Data Out, Test Clock, Test Mode Select, Test Reset are
dedicated pins for boundary-scan through the JTAG port. If JTAG is not being used,
tdi, tck, tms, and trstn should be terminated with a weak pull-up resistor. tdo can be
left unterminated. See
www.xilinx.com/partinfo/notify/pdn0007.htm
for more information.
“Terminations” on page 8
www.xilinx.com
1-800-255-7778
“Terminations” on page 8
Description
“Terminations” on page 8
“Terminations” on page 8
for more information.
for more information.
for details.
DS033 (v1.3) October 9, 2000
for more information.
for more information.
“Terminations”
R