xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 8

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

Terminations
The CoolRunner XCR3320 CPLDs are TotalCMOS™
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the lin-
ear region of the CMOS input structures, which can
increase the power consumption of the device. It can also
cause the voltage on a configuration pin to float to an
unwanted voltage level, interrupting device operation.
The XCR3320 CPLDs have programmable on-chip
pull-down resistors on each I/O pin. These pull-downs are
automatically activated by the fitter software for all unused
I/O pins. Note that an I/O macrocell used as buried logic
that does not have the I/O pin used for input is considered
to be unused, and the pull-down resistors will be turned on.
We recommend that any unused I/O pins on the XCR3320
device be left unconnected.
There are no on-chip pull-down structures associated with
dedicated pins used for device configuration or special
device functions like global reset and global 3-state. Xilinx
recommends that these pins be terminated consistent with
pin functionality. Xilinx recommends the use of weak
pull-up and pull-down resistors for terminating these pins.
See the appropriate configuration section for more informa-
tion on terminating dedicated pins.
When using the JTAG Boundary Scan functions, it is rec-
ommended that 10k
tms, tck, and trstn pins. The tdo signal pin can be left float-
ing unless it is connected to the tdi of another device. Let-
ting these signals float can cause the voltage on tms to
Table 2: Configuration Modes
DS033 (v1.3) October 9, 2000
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
R
M0
0
1
0
1
0
1
0
1
pull-up resistors be used on the tdi,
This product has been discontinued. Please see
Output
Output
Input
Input
Input
Cclk
Master serial
Slave parallel
Synchronous peripheral
Master parallel - up
Slave serial
Configuration Mode
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1-800-255-7778
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times.
Configuration Introduction
The Xilinx CoolRunner series are available in technologies
which use non-volatile (EEPROM-based) and volatile
(SRAM based) configuration memory. The functionality of
the XPLA2 family of the CoolRunner series is defined by
on-chip SRAM. The devices are configured in a manner
similar to that of most FPGAs. This section describes the
configuration of the XCR3320, and applies to all similarly
configured devices to be produced by Xilinx.
Either Xilinx or third party software is used to generate a
JEDEC file. The JEDEC file contains the configuration
data, which is loaded into the XCR3320 configuration
memory to control the XCR3320 functionality. This is done
at power-up and/or with configure command. This section
provides some of the trade-offs in selecting a configuration
mode, and provides debug hints for configuration prob-
lems.
There are several different methods of configuring the
XCR3320. The mode used is selected using the mode
select pins. There are three basic configuration methods:
master, slave, and peripheral. The configuration data can
be transmitted to the XCR3320 serially or in parallel bytes.
As a master, the XCR3320 generates the clock and control
signals to strobe configuration data into the XCR3320. As a
slave device, a clock is generated externally, and provided
into the XCR3320s cclk pin. In the peripheral mode, the
XCR3320 interfaces as a microprocessor peripheral.
Please note that M3 should always be High.
the states for the other mode pins by configuration mode.
Reserved
Reserved
Reserved
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XCR3320: 320 Macrocell SRAM CPLD
Data Format
Parallel
Parallel
Parallel
Serial
Serial
Table 2
for details.
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