xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 5

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

This product has been discontinued. Please see
XCR3320: 320 Macrocell SRAM CPLD
XPLA2 Macrocell Architecture
Figure 4
the XCR3320. The macrocell can be configured as either a
D- or T-type flip-flop or a combinatorial logic function. A
D-type flip-flop is generally more useful for implementing
state machines and data buffering while a T-type flip-flop is
generally more useful in implementing counters. Each of
these flip-flops can be clocked from any one of four
sources. Two of the clock sources (CLK0 and CLK1) are
from the eight dedicated, low-skew, global clock networks
designed to preserve the integrity of the clock signal by
reducing skew between rising and falling edges. These
clocks are designated as "synchronous" clocks and must
be driven by an external source. Both CLK0 and CLK1 can
clock the macrocell flip-flops on either the rising edge or the
falling edge of the clock signal. The other clock sources are
designated as "asynchronous" and are connected to two of
the eight control terms (CT6 and CT7) provided in each
logic block. These clocks can be individually configured as
any PRODUCT term or SUM term equation created from
the 36 signals available inside the logic block. Thus, in
each Logic Block, there are up to four possible clocks; and
in each Fast Module, there are up to ten possible clocks.
Throughout the entire device, there are up to 40 possible
clocks–eight from the dedicated, low-skew, global clocks,
and two for each of the 16 logic blocks.
The remaining six control terms of each logic block
(CT0-CT5) are used to control the asynchronous pre-
set/reset of the flip-flops and the enable/disable of the out-
put buffers in each macrocell. Control terms CT0 and CT1
are used to control the asynchronous preset/reset of the
macrocell's flip-flop. Note that the power-on reset leaves all
macrocells in the "zero" state when power is properly
Figure 4: XCR3320 Macrocell Architecture
5
shows the XPLA2 macrocell architecture used in
CLK0
CLK0
CLK1
CLK1
CT6
CT7
*SEE XPLA2 MACROCELL ARCHITECTURE DESCRIPTION
D/T
www.xilinx.com/partinfo/notify/pdn0007.htm
rstn
INIT*
www.xilinx.com
1-800-255-7778
Q
TO LZIA
applied, and that the preset/reset feature for each macro-
cell can also be disabled. Each macrocell can choose
between an asynchronous reset or an asynchronous pre-
set function, but both cannot be simultaneously used on the
same register. The global rstn function can always be used,
regardless of whether or not asynchronous reset or preset
control terms are enabled. Control terms CT2, CT3, CT4
and CT5 are used to enable or disable the macrocell's out-
put buffer. The output buffers can also be always enabled
or always disabled. All CoolRunner devices also provide a
Global 3-state (GTS) pin, which, when pulled high, will
3-state all the outputs of the device. This pin is provided to
support "In-Circuit Testin" or "Bed-of-Nails" testing used
during manufacturing.
For the macrocells in the Logic Block that are associated
with I/O pins, there are two feedback paths to the LZIA: one
from the macrocell, and one from the I/O pin. The LZIA
feedback path before the output buffer is the macrocell
feedback path, while the LZIA feedback path after the out-
put buffer is the I/O pin feedback path. When these macro-
cells are used as outputs, the output buffer is enabled, and
either feedback path can be used to feedback the logic
implemented in the macrocell. When the I/O pins are used
as inputs, the output buffer of these macrocells will be
3-stated and the input signal will be fed into the LZIA via the
I/O feedback path. In this case the logic functions imple-
mented in the buried macrocell can be fed back into the
LZIA via the macrocell feedback path. For macrocells that
are not associated with I/O pins, there is one feedback path
to the LZIA. Logic functions implemented in these buried
macrocells are fed back into the LZIA via this path. All
unused inputs and I/O pins should be properly terminated.
Please refer to
CT0
CT1
GND
GND
CT2
CT3
CT4
CT5
V
gts
CC
“Terminations” on page
for details.
GND
DS033 (v1.3) October 9, 2000
SP00590
8.
R