xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 6

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

Simple Timing Model
Figure 5
timing model is very simple compared to the models of
competing architectures. There are three main timing
parameters: the pin-to-pin delay for combinatorial logic
functions (t
and the register clock to valid output time (t
model shows, timing is only dependent on whether or not
the PLA array is used, and whether or not the logic function
is created within a single Fast Module or uses the GZIA.
The timing starts with a set time for t
Figure 5: XCR3320 Timing Module
DS033 (v1.3) October 9, 2000
shows the XCR3320 timing model. The XCR3320
PD
Within a Fast Module:
Using the Global ZIA:
), the input pin to register set up time (t
R
GLOBAL CLOCK PIN
GLOBAL CLOCK PIN
This product has been discontinued. Please see
INPUT PIN
INPUT PIN
INPUT PIN
INPUT PIN
PD
and t
t
SU_PLA
t
SU_PAL
SU
t
REGISTERED
SU_PLA
CO
= PAL + PLA + GZD
through the
REGISTERED
t
SU_PAL
= PAL + GZD
). As the
= PAL + PLA
t
PD_PLA
= PAL
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1-800-255-7778
t
t
PD_PAL
PD_PLA
SU
t
PD_PAL
= COMBINATORIAL PAL + PLA ,+ GZD
),
= COMBINATORIAL PAL + GZD
= COMBINATORIAL PAL + PLA
= COMBINATORIAL PAL
D
D
PAL array in a Fast Module, and there are fixed delays
added for use of the PLA array or the GZIA. The t
(pin-to-pin) timing specification never changes. For exam-
ple, a combinatorial logic function of four or fewer product
terms constructed from inputs within the same logic block
would have a t
more than four product terms wide, the delay would be t
plus the fixed PLA delay, or 7.5 +1.5 = 9.0 ns. A function
that used the PAL array and inputs from a different Fast
Module would have a propagation delay of t
fixed GZIA delay, or 7.5 + 2.0 = 9.5 ns.
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Q
Q
XCR3320: 320 Macrocell SRAM CPLD
REGISTERED
REGISTERED
PD
t
t
delay of 7.5 ns. If the logic function were
CO
CO
OUTPUT PIN
OUTPUT PIN
OUTPUT PIN
OUTPUT PIN
SP00591B
PD
for details.
plus the
CO
PD
6