xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 37

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

This product has been discontinued. Please see
XCR3320: 320 Macrocell SRAM CPLD
260-pin Description Table
Function is Fast Module_Logic block_Macrocell. For example, F1_0_5 means Fast Module 1, Logic block 0, Macrocell 5.
Table 16: Pin Description
37
Symbol
resetn
prgmn
mpmi
GND
done
spmi
V
cclk
din
M2
M0
M1
M3
CC
D7, D8, D10,
D11, D13,
D14, D15, G4,
G17, K4, K17,
L4, L17, P4,
P17, U6, U7,
U8, U10, U11,
U13, U14
A1, B2, B19,
C3, C18, D4,
D9, D12, D17,
J4, J17, L3,
L19, M4, M17,
U4, U9, U12,
U17, V3, V18,
W2, W19, Y20
B4
A4
D6
C4
Y5
W13
E1
N17
G18
G20
A6
Pin Numbers Type
I/O
I/O
O
O
-
-
I
I
I
I
I
Positive power supply.
Ground supply.
During configuration, resetn forces the start of initialization. After configuration,
resetn is a direct input which can be used to asynchronously reset all the flip-flops. If
the global reset is not being used, this pin should be pulled high. If the rise time of the
prgmn signal is greater than 1 microsecond, this signal must be held low until prgmn
is high.
In the master modes, cclk is an output which strobes configuration data in. In the
slave or synchronous peripheral mode, cclk is an input synchronous with the data on
din or D[7:0]. After configuration, this pin should be pulled low.
done pulling high indicates configuration is complete. As an input, a low level on done
will delay the enabling of user I/O. If only one device is used, this pin can be left
floating. If multiple devices are daisy chained, an external pull-up should be used.
prgmn is an active-low input that forces the restart of configuration and initialization
and resets the boundary-scan circuitry. After configuration, the pin should be pulled
high. This signal must have a rise time less than 1 microsecond. If the rise time of this
signal is greater than 1 microsecond, resetn must be held low until prgmn is high.
Special purpose configuration pin that must be left floating during configuration for all
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
configuration modes. After configuration the pin is a user-programmable I/O, and no
external termination is required. See
During slave serial or master serial configuration modes, din accepts serial
configuration data synchronous with cclk. During parallel configuration modes, din is
the D[0] input. After configuration, the pin is a user-programmable I/O, and no
external termination is required. See
M2/M1/M0 are used to select the configuration mode. After configuration, the pins are
user-programmable I/O, and no external termination is required. See
on page 8
M3 should be pulled high during configuration for all configuration modes. After
configuration, the pin is a user-programmable I/O, and no external termination is
required. See
done is a bi-directional signal with a weak pull-up resistor attached. As an output,
Special purpose configuration pin that must be left floating during configuration for all
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for more information.
“Terminations” on page 8
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Description
“Terminations” on page 8
“Terminations” on page 8
“Terminations” on page 8
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for details.
DS033 (v1.3) October 9, 2000
for more information.
for more information.
for more information.
“Terminations”
R