xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 14

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

Configuration Data Format
Overview
The XCR3320 functionality is determined by the state of
internal configuration RAM. This section discusses the con-
figuration data format, and the function of each field in con-
figuration data packets.
Configuration Data Packets
Configuration of the XCR3320 is done using configuration
packets. The configuration packet is shown in
The data packet consists of a header and a data frame.
There are four types of data frames. The header is shifted
into the device first, followed by one data frame. Configura-
tion of a single XCR3320 requires 338 data packets, one
for each address. All preceding data must contain only 1’s.
Once a device is configured, it retransmits data of any
polarity. Before and during configuration, all data retrans-
mitted out the daisy-chain port (dout) are 1’s.
Figure 11: Data Packet
The ordering of the data packets may be random, but they
cannot be mixed with other devices’ data packets. Align-
ment bits are not required between data packets. If used,
alignment bits must be included in the length count, and
they must be at least 2-bits long.
Table 4: Configuration Frame Size
DS033 (v1.3) October 9, 2000
Number of frames
Data bits/standard frame
Data bits/compressed frame
Data bits/user_code frame
Data bits/isc_code frame
Maximum configuration
data – # bits/frame x # frames
MSB
R
Device
DATA FRAME
This product has been discontinued. Please see
HEADER
27
XCR3320
SP00593
189280
Figure
338
560
560
560
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LSB
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1-800-255-7778
11.
Figure 12: 27-bit Header
The header is fixed and consists of five fields:
• Leading 1s,
• Preamble,
• CRC Enable,
• CRC Bits,
• Compression Bits.
The leading 1s enter the device first. The following is a
description of each field in the header.
Leading 1s:
Preamble/Postamble:
The segments CRC Enable, CRC Bits, and Compression
Bits are valid only if the Preamble field is 0010.
Cyclic Redundancy Check (CRC) Enable:
CRC Error Checking:
COMPRESSION
MSB
This is a four or greater bit field consisting of 1s.
This is a four bit field which indicates the start of a
frame or the end of configuration:
Preamble: -0010 - signals the beginning of a config-
uration data packet.
Postamble: 0100 -signals the end of configuration.
All other values of the preamble field force configu-
ration of the entire system to restart.
In this single bit field, a 0 disables CRC checking of
the data stream. If the CRC is disabled the 16 bit
CRC field must be the default described below. A1
enables CRC error checking of the data stream.
The CRC field is a 16 bit field. The default value is
1010_1010_1010_1010. The calculated value is
from data, address, stop bit, and first alignment bit
(starting with crc_reg[15:0] = [0]). Using verilog
operators, the crc is calculated as:
If a CRC error is detected, configuration is halted
and must be restarted.
BITS
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2
XCR3320: 320 Macrocell SRAM CPLD
crc_reg[14:2] <= cr_reg[14:2] << 1;
cr_reg[2] <= cr_reg[15]^din^cr_reg[1];
cr_reg[1] <= cr_reg[0];
cr_reg[0] < cr_reg[15]^din;
cr_reg[15] <= cr_reg[15]^din^cr_reg[14];
CRC
BITS
16
ENABLE
CRC
1
POSTAMBLE
PREAMBLE/
4
LEADING 1s
for details.
SP00594
4
LSB
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