adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 11

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Serial Peripheral (Compatible) Interface
The ADSP-2148x SHARC processors contain two serial periph-
eral interface ports (SPIs). The SPI is an industry-standard
synchronous serial link, enabling the SPI-compatible port to
communicate with other SPI compatible devices. The SPI con-
sists of two data pins, one device select pin, and one clock pin. It
is a full-duplex synchronous serial interface, supporting both
master and slave modes. The SPI port can operate in a multi-
master environment by interfacing with up to four other SPI-
compatible devices, either acting as a master or slave device. The
SPI-compatible peripheral implementation also features pro-
grammable baud rate and clock phase and polarities. The SPI-
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
UART Port
The processors provide a full-duplex Universal Asynchronous
Receiver/Transmitter (UART) port, which is fully compatible
with PC-standard UARTs. The UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. The UART also has multiprocessor communication capa-
bility using 9-bit address detection. This allows it to be used in
multidrop networks through the RS-485 data interface
standard. The UART port also includes support for 5 to 8 data
bits, 1 or 2 stop bits, and none, even, or odd parity. The UART
port supports two modes of operation:
The UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
Timers
The ADSP-2148x has a total of three timers: a core timer that
can generate periodic software interrupts and two general-pur-
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
• PIO (programmed I/O) – The processor sends or receives
• DMA (direct memory access) – The DMA controller trans-
• Support for bit rates ranging from (f
• Support for data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watch dog mode
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
PCLK
/16) bits per second.
PCLK
/1,048,576) to
Rev. PrA | Page 11 of 66 | March 2010
ADSP-21483/21486/21487/21488/21489
The core timer can be configured to use FLAG3 as a timer
expired signal, and the general-purpose timers have one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables the general-
purpose timer.
2-Wire Interface Port (TWI)
The TWI is a bidirectional 2-wire, serial bus used to move 8-bit
data while maintaining compliance with the I
The TWI master incorporates the following features:
I/O PROCESSOR FEATURES
The I/O processors provide up to 63 channels of DMA as well as
an extensive set of peripherals.
DMA Controller
The processor’s on-chip DMA controller allows data transfers
without processor intervention. The DMA controller operates
independently and invisibly to the processor core, allowing
DMA operations to occur while the core is simultaneously exe-
cuting its program instructions. DMA transfers can occur
between the ADSP-2148x’s internal memory and its serial ports,
the SPI-compatible (serial peripheral interface) ports, the IDP
(input data port), the parallel data acquisition port (PDAP) or
the UART. The DMA channel summary is shown in
Programs can be downloaded to the ADSP-2148x using DMA
transfers. Other DMA features include interrupt generation
upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.
Table 7. DMA Channels
1
Peripheral
SPORTs
PDAP
SPI
UART
External Port
Accelerators
Memory-to-Memory
MLB
Automotive models only.
• 7-bit addressing
• Simultaneous master and slave operation on multiple
• Digital filtering and timed event processing
• 100 kbps and 400 kbps data rates
• Low interrupt rate
device systems with support for multi master data
arbitration
1
DMA Channels
16
8
2
2
2
2
2
31
2
C bus protocol.
Table
7.