adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 48

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
SPI Interface—Slave
Table 43. SPI Interface Protocol—Slave Switching and Timing Specifications
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the processor hardware reference, “Serial Peripheral
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSOE
DSDHI
DSDHI
DDSPIDS
HDSPIDS
DSOV
Interface Port” chapter.
1
1
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0
Data Input Valid to SPICLK edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE=0)
SPIDS Assertion to Data Out Active
SPIDS Assertion to Data Out Active (SPI2)
SPIDS Deassertion to Data High Impedance
SPIDS Deassertion to Data High Impedance (SPI2)
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
Rev. PrA | Page 48 of 66 | March 2010
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
0
0
2 × t
Preliminary Technical Data
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– 2
– 2
– 2
Max
6.8
8
6.8
8.6
9.5
5 × t
PCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns