adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 46

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21483/21486/21487/21488/21489
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512 × FS clock.
Table 41. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is 64 × frame sync where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
(DATA CHANNEL
(SERIAL CLOCK)
(FRAME SYNC)
DAI_P20–1
DAI_P20–1
DAI_P20–1
LRCLK Delay After Serial Clock
LRCLK Hold After Serial Clock
Transmit Data Delay After Serial Clock
Transmit Data Hold After Serial Clock
Transmit Serial Clock Width
A/B)
Figure 34. S/PDIF Receiver Internal Digital PLL Mode Timing
DRIVE EDGE
Rev. PrA | Page 46 of 66 | March 2010
t
t
HOFSI
HDTI
t
t
DDTI
DFSI
t
SCLKIW
SAMPLE EDGE
Min
–2
–2
40
Preliminary Technical Data
Max
5
5
Unit
ns
ns
ns
ns
ns