adsp-21483 Analog Devices, Inc., adsp-21483 Datasheet - Page 47

• Manufacturer Part Number: adsp-21483
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
SPI Interface—Master
The ADSP-2148x contains two SPI ports. Both primary and sec-
ondary are available through DPI only. The timing provided in
Table 42
Table 42. SPI Interface Protocol—Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
and
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(CP = 0)
(CP = 1)
SPICLK
SPICLK
(INPUT)
(INPUT)
DPI Pin
MOSI
MISO
MOSI
MISO
Table 43
t
SSPIDM
applies to both.
Data Input Valid To SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge To Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
DPI Pin (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to DPI Pin (SPI Device Select) High
Sequential Transfer Delay
t
SDSCIM
MSB VALID
t
HSPIDM
t
t
SPICHM
SPICLM
MSB
VALID
MSB
t
SSPIDM
t
t
MSB
SPICHM
SPICLM
t
DDSPIDM
Rev. PrA | Page 47 of 66 | March 2010
t
HSPIDM
t
DDSPIDM
Figure 35. SPI Master Timing
ADSP-21483/21486/21487/21488/21489
t
HDSPIDM
LSB VALID
t
SPICLKM
LSB
LSB VALID
t
HDSPIDM
Min
8.2
2
8 × t
4 × t
4 × t
4 × t
4 × t
4 × t
4 × t
t
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
SSPIDM
t
HDSM
– 2
– 2
– 2
– 2
– 2
– 2
– 1
t
HSPIDM
LSB
t
SPITDM
Max
2.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns